HMS9XC8032 Просмотр технического описания (PDF) - Hynix Semiconductor

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HMS9XC8032

HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS

Hynix Semiconductor 

HMS91C8032/97C8032

4.1 Clock Generation Block

Software can control the system clock speed of HMS91C8032

with the SCMOD register. the SCMOD register determine sys-

tem clock speed and clock source. Figure 4-3 shows the block di-

agram of the system clock generation block.

Guideline on the CPU clock speed

For determining the speed of CPU clock(fCPU), the following

constraints should be satisfied.

The maximum counting rate of timer0~4 in counter mode,

should be less than or equal to (1/6)fCPU

The maximum timer clock rate of timer0~4 in timer mode

should be less than or equal to (1/2)fCPU

SCMOD: SELECT CLOCK MODE. : 80H

NOTE:

SCMOD[2:0]

0xx

100

101

110

111

Select system clock

fxx

fxx / 2

fxx / 4

fxx / 8

fxx / 16

-

-

-

SCSTOP SCSW SCMOD2 SCMOD1 SCMOD0

-

-

-

SCSTOP

SCSW

SCMOD2

SCMOD1

SCMOD0

SCMOD.7

SCMOD.6

SCMOD.5

SCMOD.4

SCMOD.3

SCMOD.2

SCMOD.1

SCMOD.0

Reserved for future use *

Reserved for future use *

Reserved for future use *

Software control of the main system oscillator. A logic 1 pulls down the main

system oscillator (7.2MHz).

Software switch control between main system oscillator and sub system oscillator.

A logic 1 switches sub system oscillator (32.768KHz).

See NOTES

See NOTES

See NOTES

fMOSC

(Main Oscillator Clock)

SCSTOP

fSOSC

(Sub Oscillator Clock)

0

fOSC

1 /2

(Oscillator

1 Clock)

fXX

1/2

1/4

SCSW

1/8

1/16

PLL Clock

Watchdog Clock

fCPU

(CPU Clock)

S C M O D 1,2,3

Figure 4-2 System Clock Generation Block

18

NOV., 2001 Ver 1.02

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