PM7382 Просмотр технического описания (PDF) - PMC-Sierra

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PM7382

FRAME ENGINE AND DATALINK MANAGER 32P256

PMC-Sierra 

RELEASED

DATA SHEET

PMC-2010333

ISSUE 3

PM7382 FREEDM-32P256

FRAME ENGINE AND DATA LINK MANAGER 32P256

link and 31 concatenated time-slots for an E1 link. Time-slots assigned to any

particular channel need not be contiguous within the T1/J1 or E1 link.

For unchannelised links, the FREEDM-32P256 processes up to 32 bi-directional

HDLC channels within 32 independently timed links. The links can be of

arbitrary frame format. When limited to three unchannelised links, each link can

be rated at up to 51.84 MHz provided SYSCLK is running at 45 MHz. For lower

rate unchannelised links, the FREEDM-32P256 processes up to 32 links each

rated at up to 10 MHz. In this case, the aggregate clock rate of all the links is

limited to 64 MHz.

The FREEDM-32P256 supports mixing of up to 32 channelised T1/J1/E1,

unchannelised and H-MVIP links. The total number of channels in each direction

is limited to 256. The aggregate instantaneous clock rate over all 32 possible

links is limited to 64 MHz.

In the receive direction, the FREEDM-32P256 performs channel assignment and

packet extraction and validation. For each provisioned HDLC channel, the

FREEDM-32P256 delineates the packet boundaries using flag sequence

detection, and performs bit de-stuffing. Sharing of opening and closing flags, as

well as sharing of zeros between flags are supported. The resulting packet data

is placed into the internal 32 Kbyte partial packet buffer RAM. The partial packet

buffer acts as a logical FIFO for each of the assigned channels. Partial packets

are DMA'd out of the RAM, across the PCI bus and into host packet memory.

The FREEDM-32P256 validates the frame check sequence for each packet, and

verifies that the packet is an integral number of octets in length and is within a

programmable minimum and maximum length. The receive packet status is

updated before linking the packet into a receive ready queue. The FREEDM-

32P256 alerts the PCI Host that there are packets in a receive ready queue by,

optionally, asserting an interrupt on the PCI bus.

Alternatively, in the receive direction, the FREEDM-32P256 supports a

transparent operating mode. For each provisioned transparent channel, the

FREEDM-32P256 directly transfers the received octets into host memory

verbatim. If the transparent channel is assigned to a channelised link, then the

octets are aligned to the received time-slots.

In the transmit direction, the PCI Host provides packets to transmit using a

transmit ready queue. For each provisioned HDLC channel, the FREEDM-

32P256 DMA's partial packets across the PCI bus and into the transmit partial

packet buffer. The partial packets are read out of the packet buffer by the

FREEDM-32P256 and a frame check sequence is optionally calculated and

inserted at the end of each packet. Bit stuffing is performed before being

assigned to a particular link. The flag sequence is automatically inserted when

there is no packet data for a particular channel. Sequential packets are

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 8

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