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PM4354

FOUR CHANNEL COMBINED E1/T1/J1 TRANSCEIVER/FRAMER

PMC-Sierra 

RELEASED

PM4354 COMET-QUAD

DATASHEET

PMC-1990315

ISSUE 6

FOUR CHANNEL COMBINED E1/T1/J1

TRANSCEIVER / FRAMER

alignment structure and the CRC multiframe structure may be optionally inserted. Framing can be

optionally disabled.

Internal analog circuitry allows direct transmission of long haul and short haul T1 and E1

compatible signals using a minimum of external components. Typically, only line protection, a

transformer and an optional line termination resistor are required. Digitally programmable pulse

shaping allows transmission of DSX-1 compatible signals up to 655 feet from the cross-connect,

E1 short haul pulses into 120 ohm twisted pair or 75 ohm coaxial cable, E1 long haul pulses into

120 ohm twisted pair as well as long haul DS-1 pulses into 100 ohm twisted pair with integrated

support for LBO filtering as required by the FCC rules. In addition, the programmable pulse shape

extending over 5-bit periods allows customization of short haul and long haul line interface circuits

to application requirements.

In the transmit path, the COMET-QUAD supports signaling insertion, idle code substitution, digital

milliwatt tone substitution, data inversion, and zero code suppression on a per-channel basis.

Zero code suppression may be configured to Bell (bit 7), GTE, or DDS standards, and can also be

disabled. Transmit side data and signaling trunk conditioning is also provided. Signaling bit

transparency from the backplane may be enabled.

The COMET-QUAD provides one transmit HDLC controller per channel. These controllers may

be used for the transmission of messages in the ESF data link (T1), national use bits (E1), or in

any timeslot (T1 or E1). In T1 mode, the COMET-QUAD can be configured to generate in-band

loop back codes and ESF bit oriented codes. In E1 mode, transmission of the 4-bit Sa codewords

defined in ITU-T G.704 and ETSI 300-233 is supported.

To provide for V5 applications where up to three HDLC channels are contained in each E1, the

COMET-QUAD provides a CCS H-MVIP interface. This interface allows the HDLC channels to be

inserted or extracted for external processing.

Each channel of the COMET-QUAD can generate a low jitter transmit clock from a variety of clock

references, and also provides jitter attenuation in the receive path. A low jitter recovered T1 clock

can be routed outside the COMET-QUAD for network timing applications.

Serial PCM interfaces to each T1/E1 framer allow 1.544 Mbit/s or 2.048 Mbit/s backplane

receive/backplane transmit system interfaces to be directly supported. Tolerance of gapped

clocks allows other backplane rates to be supported with a minimum of external logic.

For synchronous backplane systems, 8.192 Mbit/s H-MVIP interfaces are provided for access to

PCM data, channel associated signaling (CAS) and common channel signaling (CCS) for each T1

or E1. The CCS signaling H-MVIP interface is independent of the 64 Kbit/s PCM and CAS H-MVIP

access. The use of the H-MVIP interface requires that common clocks and frame pulse be used

along with T1/E1 elastic stores.

The COMET-QUAD is configured, controlled and monitored via a generic 8-bit microprocessor

bus through which all internal registers are accessed. All sources of interrupts can be masked

and acknowledged through the microprocessor interface.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE

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