HFBR-1119T Просмотр технического описания (PDF) - HP => Agilent Technologies

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HFBR-1119T

Fiber Optic Transmitter and Receiver Data Links for 266 MBd

HP => Agilent Technologies 

SC 25/WG3 Generic Cabling for

Customer Premises per DIS 11801

document and the EIA/TIA-568-A

Commercial Building Telecom-

munications Cabling Standard per

SP-2840.

Transmitter and Receiver

Signaling Rate Range and

BER Performance

For purposes of definition, the

symbol rate (Baud), also called

signaling rate, is the reciprocal of

the symbol time. Data rate (bits/

sec) is the symbol rate divided by

the encoding factor used to encode

the data (symbols/bit).

The specifications in this data

sheet have all been measured using

the standard Fibre Channel symbol

rate of 266 MBd.

The data link modules can be used

for other applications at signaling

rates different than specified in this

data sheet. Depending on the

actual signaling rate, there may be

some differences in optical power

budget. This is primarily caused by

a change in receiver sensitivity.

These data link modules can also

be used for applications which

require different bit-error-ratio

(BER) performance. Figure 5

illustrates the typical trade-off

between link BER and the receiver

input optical power level.

Data Link Jitter

Performance

The Hewlett-Packard 1300 nm data

link modules are designed to

operate per the system jitter

allocations stated in FC-PH Annex

A.4.3 and A.4.4.

The 1300 nm transmitter will

tolerate the worst-case input

electrical jitter allowed, without

violating the worst-case output

optical jitter requirements.

1 x 10-2

1 x 10-3

1 x 10-4

1 x 10-5

1 x 10-6

1 x 10-7

1 x 10-8

1 x 10-9

1 x 10-10

1 x 10-11

1 x 10-12

-6

CENTER OF SYMBOL

-4

-2

0

2

RELATIVE INPUT OPTICAL POWER – dB

CONDITIONS:

1. 266 MBd

2. PRBS 27-1

3. TA = 25 °C

4. VCC = 5 Vdc

5. INPUT OPTICAL RISE/FALL TIMES =

1.0/1.9 ns

Figure 5. HFBR-1119T/2119T Bit-

Error-Ratio vs. Relative Receiver

Input Optical Power.

Care should be taken to avoid

shorting the receiver Data or

Signal Detect Outputs directly to

ground without proper current-

limiting impedance.

Solder and Wash Process

Compatibility

The transmitter and receiver are

delivered with protective process

caps covering the individual ST*

ports. These process caps protect

the optical subassemblies during

wave solder and aqueous wash

processing and act as dust covers

during shipping.

These data link modules are

compatible with either industry

standard wave- or hand-solder

processes.

The 1300 nm receiver will tolerate

the worst-case input optical jitter

allowed without violating the

worst-case output electrical jitter

allowed.

The jitter specifications stated in

the following transmitter and

receiver specification tables are

derived from the values in FC-PH

Annex A.4.3 and A.4.4. They

represent the worst-case jitter

contribution that the transmitter

and receiver are allowed to make

to the overall system jitter without

violating the allowed allocation. In

practice, the typical jitter contribu-

tion of the Hewlett-Packard data

link modules is well below the

maximum allowed amounts.

Recommended Handling

Precautions

It is advised that normal static pre-

cautions be taken in the handling

and assembly of these data link

modules to prevent damage which

may be induced by electrostatic

discharge (ESD). The HFBR-1119/

-2119 series meets MIL-STD-883C

Method 3015.4 Class 2.

Shipping Container

The data link modules are

packaged in a shipping container

designed to protect it from

mechanical and ESD damage

during shipment or storage.

Board Layout–Interface

Circuit and Layout

Guidelines

It is important to take care in the

layout of your circuit board to

achieve optimum performance

from these data link modules.

Figure 6 provides a good example

of a power supply filter circuit that

works well with these parts. Also,

suggested signal terminations for

the Data, Data-bar, Signal Detect

and Signal Detect-bar lines are

shown. Use of a multilayer,

ground-plane printed circuit board

will provide good high-frequency

circuit performance with a low

inductance ground return path. See

additional recommendations noted

in the interface schematic shown in

Figure 6.

203

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