ATT3042 Просмотр технического описания (PDF) - Unspecified

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ATT3042

Field-Programmable Gate Arrays

Unspecified 

Data Sheet

February 1997

ATT3000 Series Field-Programmable Gate Arrays

Pin Information (continued)

Table 5. I/O Pins with Special Functions

Symbol

M2

HDC

LDC

INIT

BCLKIN

XTL1

XTL2

CS0, CS1,

CS2, WS

Name/Description

Mode 2. This input has a passive pull-up during configuration. Together with M0 and M1, it is

sampled before the start of configuration to establish the configuration mode to be used. After

configuration, this pin becomes a user-programmable I/O pin.

High During Configuration. HDC is held at a high level by the FPGA until after configuration. It

is available as a control output indicating that configuration is not yet completed. After

configuration, this pin is a user I/O pin.

Low During Configuration. This active-low signal is held at a low level by the FPGA until after

configuration. It is available as a control output indicating that configuration is not yet completed.

It is particularly useful in master mode as a low enable for an EPROM. After configuration, this

pin is a user I/O pin. If used as a low EPROM enable, it must be programmed as a high after

configuration.

This is an active-low, open-drain output which is held low during the power stabilization and

internal clearing of the configuration memory. It can be used to indicate status to a configuring

microprocessor or, as a wired-AND of several slave mode devices, a hold-off signal for a master

mode device. After configuration, this pin becomes a user-programmable I/O pin.

This is a direct CMOS level input to the alternate clock buffer (auxiliary buffer) in the lower right

corner.

This user I/O pin can be used to operate as the output of an amplifier driving an external crystal

and bias circuitry.

This user I/O pin can be used as the input of an amplifier connected to an external crystal and

bias circuitry. The I/O block is left unconfigured. The oscillator configuration is activated by

routing a net from the oscillator buffer symbol output and by the ORCA Foundry bit stream

generation program.

These four inputs represent a set of signals, three active-low and one active-high, which are

used in the peripheral mode to control configuration data entry. The assertion of all four

generates a write to the internal data buffer. The removal of any assertion clocks in the D[7:0]

data present. In the master parallel mode, WS and CS2 are the A0 and A1 outputs. After

configuration, the pins are user-programmable I/O pins.

Lucent Technologies Inc.

35

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