ADSP-2186L
TIMING PARAMETERS
Parameter
Min
Max
Unit
Clock Signals and Reset
Timing Requirements:
tCKI
tCKIL
tCKIH
CLKIN Period
CLKIN Width Low
CLKIN Width High
50
150
ns
20
ns
20
ns
Switching Characteristics:
tCKL
CLKOUT Width Low
0.5 tCK – 7
ns
tCKH
CLKOUT Width High
0.5 tCK – 7
ns
tCKOH
CLKIN High to CLKOUT High
0
20
ns
Control Signals
Timing Requirements:
tRSP
RESET Width Low1
5 tCK
ns
tMS
Mode Setup before RESET High
2
ns
tMH
Mode Setup after RESET High
5
ns
NOTE
1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
CLKIN
CLKOUT
PF(2:0)*
RESET
tCKI
tCKIH
tCKIL
tCKOH
tCKH
tCKL
tMS
tMH
*PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A
tRSP
Figure 11. Clock Signals
–16–
REV. B