Z8018010VEC Просмотр технического описания (PDF) - Zilog
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Z8018010VEC Datasheet PDF : 70 Pages
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Zilog
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
TIMING DIAGRAMS
Opcode fetch Cycle
I/O Write Cycle *2
T1
T2
TW
T3
I/O Read Cycle *2
T1
T2
TW
T3
T1
1
23
4
5
ø
1
6
ADDRESS
/WAIT
19 20 19 20
7
/MREQ
8
/IORQ
/RD
9
/WR
/M1
12 11
7
11
13
28
9 22
14
29 11
13
11
25
10
ST
17
Data IN
Data OUT
62
63
/RESET
18
15
16
24
23
15 16 21
27
*1
62
63
68
67
67
68
Notes:
*1. Output buffer is off at this point.
*2. Memory Read/Write Cycle timing are the same as I/O Read/Write Cycle except
there are no automatic wait states (TW), and /MREQ is active instead of /IORQ.
Figure 20. CPU Timing
(Opcode Fetch Cycle, Memory Read Cycle,
Memory Write Cycle, I/O Write Cycle, I/O Read Cycle)
DS971800401
PRELIMINARY
1-29
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