ADM1026JST-REEL7 Просмотр технического описания (PDF) - ON Semiconductor

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ADM1026JST-REEL7

Complete Thermal System Management Controller

ON Semiconductor 

ADM1026

2. Data is sent over the serial bus in sequences of nine

clock pulses, 8 bits of data followed by an

acknowledge bit from the slave device. Data

transitions on the data line must occur during the

low period of the clock signal and remain stable

during the high period, because a low−to−high

transition when the clock is high may be interpreted

as a stop signal.

If the operation is a write operation, the first data

byte after the slave address is a command byte.

This tells the slave device what to expect next. It

may be an instruction telling the slave device to

expect a block write, or it may simply be a register

address that tells the slave where subsequent data is

to be written.

Because data can flow in only one direction as

defined by the R/W bit, it is not possible to send a

command to a slave device during a read operation.

1

91

SCL

Before doing a read operation, it may first be

necessary to do a write operation to tell the slave

what type of read operation to expect and/or the

address from which data is to be read.

3. When all data bytes have been read or written, stop

conditions are established. In write mode, the master

pulls the data line high during the 10th clock pulse

to assert a stop condition. In read mode, the master

device releases the SDA line during the low period

before the ninth clock pulse, but the slave device

does not pull it low (called No Acknowledge). The

master takes the data line low during the low period

before the 10th clock pulse, then high during the

10th clock pulse to assert a stop condition.

*If it is required to perform several read or write operations in

succession, the master can send a repeat start condition

instead of a stop condition to begin a new operation.

9

SDA

0

1

START BY

MASTER

0

1

1 A1 A0 R/W

D7 D6 D5 D4 D3 D2 D1 D0

FRAME 1

SLAVE ADDRESS

ACK. BY

SLAVE

FRAME 2

COMMAND CODE

ACK. BY

SLAVE

1

9

1

9

SCL

(CONTINUED)

SDA

(CONTINUED)

1

SCL

D7 D6 D5 D4 D3 D2 D1 D0

FRAME 3

DATA BYTE

ACK. BY

SLAVE

D7 D 6 D5 D4 D3 D2 D1 D0

FRAME N

DATA BYTE

ACK. BY STOP BY

SLAVE MASTER

Figure 16. General SMBus Write Timing Diagram

91

9

SDA

0

START BY

MASTER

1

0

1

1

A1 A0 R/W

D7 D6 D5 D4 D3 D2 D1 D0

FRAME 1

SLAVE ADDRESS

ACK. BY

SLAVE

FRAME 2

DATA BYTE

ACK. BY

MASTER

1

9

1

9

SCL

(CONTINUED)

SDA

(CONTINUED)

D7 D6 D5 D4 D3 D2 D1 D0

FRAME 3

DATA BYTE

ACK. BY

MASTER

D7 D 6 D5 D4 D3 D2 D1 D0

FRAME N

DATA BYTE

NO ACK.

STOP BY

MASTER

Figure 17. General SMBus Read Timing Diagram

SMBus Protocols for RAM and EEPROM

The ADM1026 contains volatile registers (RAM) and

non−volatile EEPROM. RAM occupies Addresses 00h to

6Fh, while EEPROM occupies Addresses 8000h to 9FFFh.

Data can be written to and read from both RAM and

EEPROM as single data bytes and as block (sequential) read

or write operations of 32 data bytes, the maximum block size

allowed by the SMBus specification.

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