80960MC(2004) Просмотр технического описания (PDF) - Intel

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производитель

80960MC
(Rev.:2004)

EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT

Intel 

80960MC

CLK2

PREVIOUS

CYCLE

INTERRUPT

ACKNOWLEDGEMENT

CYCLE 1

TX

TX Ta Td

Tr

IDLE

(5 BUS STATES)

TI

TI

TI

TI

INTERRUPT

ACKNOWLEDGEMENT

CYCLE 2

TI

Ta

Tw

Td Tr

CLK

INTR

LAD31:0

ALE

ADS

INTA

DT/R

ADDR

ADDR

VECTO R

DEN

LOCK

READY

NOTE:

INTR can go low no sooner than the input hold time following the beginning of interrupt acknowledgment cycle 1.

For a second interrupt to be acknowledged, INTR must be low for at least three cycles before it can be reasserted.

Figure 27. Interrupt Acknowledge Transaction

34

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