ADRF6510 Просмотр технического описания (PDF) - Analog Devices

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ADRF6510

30 MHz Dual Programmable Filters and Variable Gain Amplifiers

Analog Devices 

ADRF6510

THEORY OF OPERATION

The ADRF6510 consists of a matched pair of buffered, program-

mable filters followed by variable gain amplifiers and output

ADC drivers. The block diagram of a single channel is shown

in Figure 41. The programmability of the bandwidth and of the

pre- and post-filtering gain offers great flexibility when coping

with signals of varying levels in the presence of noise and large,

undesired signals nearby. The entire differential signal chain is

dc-coupled with flexible interfaces at the input and output. The

bandwidth and gain setting controls for the two channels are

shared, ensuring close matching of their magnitude and phase

responses. The ADRF6510 can be fully disabled through the

ENBL pin.

6dB/12dB

PREAMP

1MHz TO 30MHz 50dB

PROG. FILTERS VGA

OUTPUT ADC

DRIVER

BASEBAND

INPUTS

BASEBAND

OUTPUTS

PREAMP

GAIN SWITCH

SPI

INTERFACE

FILTER

PROGRAMMING

SPI BUS

ANALOG

GAIN CONTROL

30mV/dB

OUTPUT

COMMON-MODE

CONTROL

Figure 41. Signal Path Block Diagram for a Single Channel of the ADRF6510

Filtering and amplification are fundamental operations in any

signal processing system. Filtering is necessary to select the

intended signal while rejecting out-of-band noise and interferers.

Amplification increases the level of the desired signal to overcome

noise added by the system. When used together, filtering and

amplification can extract a low level signal of interest in the

presence of noise and out-of-band interferers. Such analog

signal processing alleviates the requirements on the analog,

mixed signal, and digital components that follow.

INPUT BUFFERS

The input buffers provide a convenient interface to the sensitive

filter sections that follow. They set a differential input impedance

of 400 Ω and sit at a nominal common-mode voltage of VPS/2.

The inputs can be dc-coupled or ac-coupled. If using direct

dc-coupling, the common-mode voltage, VCM, can range from

1.5 V to 3 V. A current flows into or out of the input pins to

accommodate the difference in common-mode voltages. The

current into each pin is given by

(VCM – (VPS/2))/200 Ω

The input buffers in both channels can be configured simulta-

neously to a gain of 6 dB or 12 dB through the GNSW pin. When

configured for a 6 dB gain, the buffers support up to a 1 V p-p

differential input level with >50 dBc harmonic distortion. For

a 12 dB gain setting, the buffers support 0.5 V p-p inputs.

PROGRAMMABLE FILTERS

The integrated programmable filter is the key signal processing

function in the ADRF6510. The filters follow a six-pole Butter-

worth prototype response that provides a compromise between

band rejection, ripple, and group delay. The 0.5 dB bandwidth is

programmed from 1 MHz to 30 MHz in 1 MHz steps via the serial

programming interface (SPI) as described in the Programming

the Filters section.

The filters are designed so that the Butterworth prototype filter

shape and group delay responses vs. frequency are retained for

any bandwidth setting. Figure 42 and Figure 43 illustrate the

ideal six-pole Butterworth gain and group delay responses,

respectively. The group delay, τg, is defined as

τg = −∂φ/∂ω

where:

φ is the phase in radians.

ω = 2πf is the frequency in radians/second.

Note that for a frequency scaled filter prototype, the absolute

magnitude of the group delay scales inversely with the band-

width; however, the shape is retained. For example, the peak

group delay for a 28 MHz bandwidth setting is 14× less than

for a 2 MHz setting.

0

–20

–40

–60

–80

–100

–120

–140

–160

–180

1M

10M

100M

1G

FREQUENCY (Hz)

Figure 42. Sixth-Order Butterworth Magnitude Response for 0.5 dB

Bandwidths; Programmed from 2 MHz to 29 MHz in 1 MHz Steps

500

400

2MHz

28MHz

300

200

14x

100

0

–100

100k

1M

10M

FREQUENCY (Hz)

100M

Figure 43. Sixth-Order Butterworth Group Delay Response for

0.5 dB Bandwidths; Programmed to 2 MHz and 28 MHz

Rev. 0 | Page 14 of 28

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