CY8C24693-24LQXI Просмотр технического описания (PDF) - Cypress Semiconductor
Номер в каталоге
Компоненты Описание
производитель
CY8C24693-24LQXI Datasheet PDF : 65 Pages
| |||
CY8C24X93
Pinouts
16-pin QFN (13 GPIOs) [2]
Table 2. Pin Definitions – CY8C24093 [3]
Pin
No.
Type
Name
Digital Analog
Description
1 I/O
I
P2[5] Crystal output (XOut)
2 I/O
3 IOHR
4 IOHR
I
P2[3] Crystal input (XIn)
I
P1[7] I2C SCL, SPI SS
I
P1[5] I2C SDA, SPI MISO
5 IOHR
6 IOHR
I
P1[3] SPI CLK
I
P1[1] ISSP CLK[4], I2C SCL, SPI
MOSI
7
Power
8 IOHR
I
VSS Ground connection
P1[0] ISSP DATA[4], I2C SDA, SPI
CLK[5]
9 IOHR
I
P1[2]
10 IOHR
I
P1[4] Optional external clock
(EXTCLK)
11
Input
XRES Active high external reset with
internal pull-down
12 IOH
I
P0[4]
13
Power
14 IOH
I
VDD Supply voltage
P0[7]
15 IOH
I
P0[3]
16 IOH
I
P0[1]
Figure 1. CY8C24093 Device
AI , XOut, P2[5]
AI , XIn, P2[3]
AI , I2 C SCL, SPI SS, P1[7]
AI , I2 C SDA, SPI MISO, P1[5]
1
12
2 QFN 11
3 (Top View)10
4
9
P0[4] , AI
XRES
P1[4] , EXTCLK, AI
P1[2] , AI
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
2. No center pad.
3. 13 GPIOs.
4. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive
resistive
low
low
for
for
512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL
8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the
lIi2nCesbdusri.veUse
alternate pins if you encounter issues.
5. Alternate SPI clock.
Document Number: 001-86894 Rev. *B
Page 10 of 65
Share Link: 