DAC8248FW Просмотр технического описания (PDF) - Analog Devices

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DAC8248FW

Dual 12-Bit (8-Bit Byte) Double-Buffered CMOS D/A Converter

Analog Devices 

DAC8248

INTERFACE CONTROL LOGIC PIN FUNCTIONS

LSB/MSB – (PIN 17) LEAST SIGNIFICANT BIT (Active

Low)/ MOST SIGNIFICANT BIT (Active High). Selects

lower 8-bits (LSBs) or upper 4-bits (MSBs); either can be

loaded first. It is used with the WR signal to load data into the

input registers. Data is loaded in a right justified format.

DAC A/DAC B – (PIN 18) DAC SELECTION. Active low

for DAC A and Active High for DAC B.

WR – (PIN 20) WRITE – Active Low. Used with the LSB/

MSB signal to load data into the input registers, or Active High

to latch data into the input registers.

LDAC – (PIN 19) LOAD DAC. Used to transfer data sim-

ultaneously from DAC A and DAC B input registers to both

DAC output registers. The DAC register becomes transparent

(activity on the digital inputs appear at the analog output) when

both WR and LDAC are low. Data is latched into the output

registers on the rising edge of LDAC.

RESET – (PIN 16) – Active Low. Functions as a zero over-

ride; all registers are forced to zero when the RESET signal is

low. All registers are latched to zeros when the write signal is

high and RESET goes high.

APPLICATIONS INFORMATION

UNIPOLAR OPERATION

Figure 7 shows a simple unipolar (2-quadrant multiplication)

circuit using the DAC8248 and OP270 dual op amp (use two

OP42s for applications requiring higher speeds), and Table I

shows the corresponding code table. Resistors R1, R2, and R3,

R4 are used only if full-scale gain adjustments are required.

Table I. Unipolar Binary Code Table (Refer to Figure 7)

Binary Number in

DAC Register

MSB

LSB

Analog Output, VOUT

(DAC A or DAC B)

1111 1111 1111

 4095 

–VREF  4096 

1000 0000 0000

 2048  1

–VREF  4096  = – 2 VREF

0000 0000 0001

0000 0000 0000

 1

–VREF  4096 

0V

NOTE

1 LSB = (2-12) (VREF)=

1

4096

(VREF)

Low temperature-coefficient (approximately 50 ppm/°C) resis-

tors or trimmers should be used. Maximum full-scale error

without these resistors for the top grade device and VREF =

± 10 V is 0.024%, and 0.049% for the low grade. Capacitors C1

and C2 provide phase compensation to reduce overshoot and

ringing when high-speed op amps are used.

Full-scale adjustment is achieved by loading the appropriate

DAC’s digital inputs with 1111 1111 1111 and adjusting R1 (or

R3 for DAC B) so that:

VOUT

=

VREF

×





4095 

4096 

Full-scale can also be adjusted by varying VREF voltage and

eliminating R1, R2, R3, and R4. Zero adjustment is performed by

Figure 7. Unipolar Configuration (2-Ouadrant Multiplication)

–12–

REV. B

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