MT90737 Просмотр технического описания (PDF) - Mitel Networks
Номер в каталоге
Компоненты Описание
производитель
MT90737 Datasheet PDF : 40 Pages
| |||
Preliminary Information
CMOS MT90737
Register Bit Map Definitions
Addr Bit
Symbol
Description
00 7
6
5
4
R3LOS
R3OOF
R3AIS
R3IDL
Receive DS3 Loss of Signal. A receive LOS alarm occurs (R3LOS is set to 1)
when the incoming DS3 data (DS3DR) is stuck low for more than 1022 clock
cycles (DS3CR). Recovery occurs (R3LOS is reset to 0) when two or more ones
are detected in the incoming data bit stream. This bit position is unlatched.
Receive DS3 Out of Frame. A receive OOF alarm occurs (R3OOF is set to 1)
when three out of 16 F-bits are in error in a sliding window of 16 bits, or one or
more M-bits are in error in two consecutive frames. Recovery occurs (R3OOF is
reset to 0) when the F-bits pattern of 1001 and the M-bits of 010 are detected for
two consecutive frames. Recovery takes approximately 0.95 milliseconds, worst
case. This bit position is unlatched. An OOF also inhibits the performance counters
(04H, 05H, 06H, 1BH, 22H, and 23H).
Receive AIS Alarm Indication Signal. The MT90737 can detect one of six possi-
ble DS3 AIS’s including the ANSI’s standard AIS pattern. An 1 in R3AIS indicates a
receive AIS has been detected. The pattern of AIS is selected by the states written
to the three R3AISn bits in register 21H. R3AIS bit position is unlatched. When the
MT90737 is configured to detect one of the framed AIS signals, the R3OOF (bit 6
of this register) should be examined to ensure that the MT90737 is detecting DS3
frame.
Receive DS3 Idle Pattern Signal. A DS3 idle pattern signal has the valid M-bit, F-
bit, and P-bit channels. The information bits are a 1100 sequence that starts with
11 after each M-bit, F-bit, X-bit, P-bit, and C-bit channels. The C-bits (C7, C8, and
C9) in M-subframe 3 are set to zero.
A valid received DS3 idle signal is detected when the MT90737 detects zeros for
C7, C8, and C9 in subframe 3 and the 1100 sequence. The 1100 pattern sequence
is searched on a per DS3 frame basis. The MT90737 can tolerate up to and includ-
ing 5 errored 4 bit groups of the 1100 pattern per DS3 frame and still recognize the
1100 pattern as valid. If the MT90737 detects 6 or more errored 4 bit groups of the
1100 pattern per DS3 frame the MT90737 will exit the R3IDL state. This bit position
is unlatched.
A DS3 idle signal as defined in ANSI T1.107a-1990 is being received by the
MT90737 device if this bit (R3IDL), bit 1 (XR2) and bit 0 (XR1) of this register are
all set to 1.
3
R3CKF Receive DS3 Clock Failure. A receive DS3 clock failure alarm occurs (R3CKF is
set to 1) when the receive clock (DS3CR) is stuck high or low for 30-100 DS3 clock
periods. The demultiplexer does not function when the receive clock is lost. Recov-
ery occurs on the first clock transition. This bit position is unlatched.
2
T3CKF Transmit DS3 Clock Failure. A transmit DS3 clock failure alarm occurs (T3CKF is
set to 1) when the transmit input clock (XCK) is stuck high or low for 30-100 DS3
clock periods. A failure causes the receive clock to become the transmit clock. This
permits the MT90737 microprocessor interface and multiplexer to function. Recov-
ery occurs when the first clock transition is detected.
1
XR2 Receive DS3 X-bit Number 2. This bit position indicates the receive state of X2.
This bit position is updated each frame.
0
XR1 Receive DS3 X-bit Number 1. This bit position indicates the receive state of X1.
This bit position is updated each frame.
5-75
Share Link: 