Z801806PSC Просмотр технического описания (PDF) - Zilog

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производитель

Z801806PSC

Microprocessor Unit

Zilog 

Z80180

Microprocessor Unit

55

DMA Source Address Register, Channel 0H

Mnemonic SAR0H: Address 21h

Timer Data Register

76 54 32 1 0

—— —— — — — —

DMA Channel 0 Address

Figure 49. DMA Channel 0H

DMA Source Address Register Channel 0B

Mnemonics SAR0B: Address 22h

Timer Data Register

76 54 32 1 0

—— —— — — — —

DMA Channel B Address

Figure 50. DMA Channel 0B

DMA Destination Address Register Channel 0

(DAR0: I/O ADDRESS = 23h to 25h) specifies the physical destination address for channel 0

transfers. The register contains 20 bits and can specify up to 1024 KB memory addresses or

up to 64 KB I/O addresses. Channel 0 destination can be memory, I/O, or memory mapped I/

O. For I/O, the most significant bits of this register identify the REQUEST HANDSHAKE

signal for channel 0.

PS014004-1106

Architecture

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