XE1202A Просмотр технического описания (PDF) - Semtech Corporation

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XE1202A

433 MHz / 868 MHz / 915 MHz Low-Power, Integrated UHF Transceiver

Semtech Corporation 

XE1202A TrueRF™

When the “RTParam_Clkout” bit is set high, FXTAL is frequency divided by 4, 8, 16, or 32, depending on the value

of register “ADParam_Clkfreq” (see the Configuration register section below), and made available as CLKOUT, for

use as clock signal for an MCU or external circuitry. If the reference frequency is 39 MHz, the available output

frequency of CLKOUT is 1.22, 2.44, 4.87, or 9.75 MHz, respectively. When the XE1202A TrueRF™ is in Sleep

Mode (MODE[2:0] = 000), CLKOUT is disabled.

5 Serial Interface Definition, Principles of Operation

5.1 Serial Control Interface

5.1.1 General description

A 3-wire bi-directional bus (SCK, SI, SO) is used to program the XE1202A TrueRF™ and read data from it. SCK

and SI are input signals, for example generated by a microcontroller. SO is an output signal controlled by the

XE1202A TrueRF™. In write mode, at the falling edge of the SCK signal, the logic data on the SI line is written into

an internal shift register. In read mode, at the rising edge of the SCK signal, the data on the SO line becomes valid

and should be sampled at the next falling edge of SCK.

The signal /EN must be low during the complete write and read sequences. In write mode the actual content of the

configuration register is updated at the rising edge of the /EN signal. Before this, the new data is stored in

temporary registers whose content does not affect the transceiver settings.

5.1.2 Write sequence

The time diagram of a write sequence is illustrated in Figure 7 below. This sequence is initiated when a Start

condition is detected, defined by the SI signal being set to “0” during a period of SCK. The next bit is a read/write

(R/W) bit which should be “0” to indicate a write operation. The next 5 bits are the address of the control register

A[4:0] to be accessed, MSB first. Then the next 8 bits contain the data to be written in the register. The sequence

ends with 2 stop bits set to “1”. The data on SI should change at the rising edges of SCK, and is sampled at the

falling edge of SCK. After the 2 stop bits, the data transfer is terminated, even if the SI line stays at “1”. After this

the SI line should be at “1” for at least one clock cycle on SCK before a new write or read sequence can start. This

mode of operation allows data to be written to multiple registers without the need to alter the status of EN.

The maximum frequency of SCK is 1 MHz. The minimum clock pulse width is 0.5us. Set-up and hold time for SI on

the falling edge of SCK is 200 ns, over the operating supply and temperature range.

SCK

SI

START R/W A(4)

A(1) A(0) D(7) D(6)

D(3) D(2) D(1) D(0) STOP STOP

SO

/EN

5.1.3 Read sequence

Figure 7: Write sequence into configuration register

The time diagram of a read sequence is illustrated in Figure 8. The sequence is initiated when a Start condition is

detected, defined by the SI signal being set to “0” during a period of SCK. The next bit is a read/write (R/W) bit

which should be “1” to indicate a read operation. The next 5 bits are the address of the control register A[4:0] to be

accessed, MSB first. The data from the register is then output on the SO pin.

The data becomes valid at the rising edges of SCK and should be sampled at the falling edge of SCK. After this the

data transfer is terminated. The SI line must stay high for at least one clock cycle on SCK to start a new write or

read sequence. The maximum current drive on SO is 2 mA for a supply voltage of 2.7 V, and the maximum load is

CLop, as defined in the Electrical Specifications.

© Semtech 2006

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