CS8412 Просмотр технического описания (PDF) - Unspecified

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CS8412

Digital Audio Interface Receiver

Unspecified 

CS8411 CS8412

data can be read twice or missed if the device con-

trolling FSYNC and SCK is on a different time-

base than the CS8411. If the audio data is read

twice or missed, the SLIP bit in SR1 is set. SCED

selects the SCK edge to output data on. SCED high

causes data to be output on the falling edge, and

SCED low causes data to be output on the rising

edge.

Audio Serial Port

The audio serial port outputs the audio data portion

from the received data and consists of three pins:

SCK, SDATA, and FSYNC. SCK clocks the data

out on the SDATA line. The edge that SCK uses to

output data is programmable from CR2. FSYNC

delineates the audio samples and may indicate the

particular channel, left or right. Figure 10 illus-

trates the multitude of formats that SDATA and

FSYNC can take.

Normal Modes

SCK and FSYNC can be inputs (MSTR = 0) or out-

puts (MSTR = 1), and are usually programmed as

outputs. As outputs, SCK contains 32 periods for

FSF MSTR

10 (bit)

00 0 FSYNC Input

01 0 FSYNC Input

32 Bits

32 Bits

10 0 FSYNC Input

11 0 FSYNC Input

00 1 FSYNC Output

01 1 FSYNC Output

10 1 FSYNC Output

11 1 FSYNC Output

SDF

210 (bit) Name

000

MSB First - 32

001

MSB Last

011

LSB Last - 16

101

LSB Last - 18

111

LSB Last - 20

SPECIAL MODES:

SDF

210 MSTR Name

100 0 Async SCK

110 0 MSB First - 24

010 0 MSB First - 16

010* 1 NRZ Data

16 Clocks

16 Clocks

16 Clocks

16 Clocks

32 Clocks

32 Clocks

MSB

MSB

LSB

LSB

LSB

32 Clocks

Left Sample

24 Bits, Incl. Aux

LSB

24 Bits, Incl. Aux

LSB

16 Bits

MSB

18 Bits

MSB

20 Bits

MSB

MSB

MSB

LSB

LSB

LSB

32 Clocks

Right Sample

24 Bits, Incl. Aux

LSB

24 Bits, Incl. Aux

LSB

16 Bits

MSB

18 Bits

MSB

MSB

20 Bits

MSB

MSB

LSB

LSB

LSB

24 Bits, Incl. Aux

24 Bits, Incl. Aux

MSB

LSB

MSB

LSB

MSB

24 Bits, Incl. Aux

24 Bits, Incl. Aux

MSB

LSB MSB

LSB MSB

16 Bits

16 Bits

MSB

LSB MSB

LSB MSB

32 Bits

32 Bits

AUX LSB

MSB VUCP

AUX LSB

MSB VUCP

AUX

100* 1 Bi-Phase Data

Bi-Phase Mark Data

Bi-Phase Mark Data

* Error flags are not accurate in these modes

Figure 10. CS8411 Serial Port SDATA and FSYNC Timing

DS61F1

13

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