Block Diagram and Pin Configuration
(Top View)
10 9 8 7 6 5 4 3 2 1
ICX205AL
Horizontal register
Note)
Note)
: Photo sensor
11 12 13 14 15 16 17 18 19 20
Pin Description
Pin No. Symbol
Description
1
Vφ1
Vertical register transfer clock
2
Vφ2A
Vertical register transfer clock
3
Vφ2B
Vertical register transfer clock
4
Vφ3
Vertical register transfer clock
5 NC
6 NC
7 GND GND
8 NC
9 GND GND
10
VOUT
Signal output
Pin No. Symbol
Description
11
VDD
Supply voltage
12 GND GND
13 φSUB Substrate clock
14 NC
15
CSUB
Substrate bias∗1
16 NC
17 VL
Protective transistor bias
18 φRG Reset gate clock
19 Hφ1
Horizontal register transfer clock
20 Hφ2
Horizontal register transfer clock
∗1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance
of 0.1µF.
–2–