X4003M8IZ-2.7A Просмотр технического описания (PDF) - Intersil

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Компоненты Описание

производитель

X4003M8IZ-2.7A

CPU Supervisor

Intersil 

X4003, X4005

TIMING DIAGRAMS

Bus Timing

SCL

SDA IN

tSU:STA

tF

tHIGH

tSU:DAT

tHD:STA

tLOW

tHD:DAT

SDA OUT

tR

tA

tDH

WP Pin Timing

SCL

SDA IN

WP

Start

Clk 1

Slave Address Byte

Clk 9

tSU:WP

tHD:WP

tSU:STO

tBUF

Write Cycle Timing

SCL

SDA

8th Bit of Last Byte

ACK

tWC

Stop

Condition

Start

Condition

Nonvolatile Write Cycle Timing

Symbol

tWC(7)

Parameter

Write cycle time

Min.

Typ.(1)

5

Max.

10

Unit

ms

Note: (7) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is

the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

14

FN8113.1

May 11, 2006

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