WM8973 Просмотр технического описания (PDF) - Wolfson Microelectronics plc
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WM8973 Datasheet PDF : 63 Pages
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WM8973L
CONTROL INTERFACE TIMING – 3-WIRE MODE
CSB
tCSL
SCLK
tSCY
tSCH
tSCL
Production Data
tCSH
tSCS
tCSS
SDIN
tDSU
tDHO
LSB
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
CSB pulse width high
CSB rising to SCLK rising
Pulse width of spikes that will be suppressed
tSCS
tSCY
tSCL
tSCH
tDSU
tDHO
tCSL
tCSH
tCSS
tps
80
200
80
80
40
40
40
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
ns
w
PD, Rev 4.5, December 2011
16
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