WM8580 Просмотр технического описания (PDF) - Wolfson Microelectronics plc

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WM8580

Multichannel CODEC with S/PDIF Transceiver

Wolfson Microelectronics plc 

WM8580

Production Data

CONTROL INTERFACE OPERATION

Control of the WM8580 is implemented either in Hardware Control Mode or Software Control Mode.

The method of control is determined by the state of the HWMODE pin. If the HWMODE pin is low,

Software Control Mode is selected. If the HWMODE pin is high, Hardware Control Mode is selected.

The Software Control Interface is described below and Hardware Control Mode is described on page

70

Software control is implemented with a 3-wire (3-wire write, 4-wire read, SPI compatible) or 2-wire

read/write serial interface.

The interface configuration is determined by the state of the SWMODE pin. If the SWMODE pin is

low, the 2-wire configuration is selected. If SWMODE is high the 3-wire SPI compatible configuration

is selected.

HWMODE

0

1

Software Control Hardware Control

SWMODE

0

1

2-wire control 3-wire control

Table 8 Hardware/Software Mode Setup

The control interface is 5V tolerant, meaning that the control interface input signals CSB, SCLK and

SDIN may have an input high level of 5V while DVDD is 3V. Input thresholds are determined by

DVDD.

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE WITH READ-BACK

SDIN is used to program data, SCLK is used to clock in the program data and CSB is used to latch

the program data. SDIN is sampled on the rising edge of SCLK. The 3-wire interface write protocol is

shown in Figure 6.

Figure 6 3-Wire SPI Compatible Interface

1. A[6:0] are Control Address Bits

2. D[8:0] are Control Data Bits

3. CSB is edge sensitive – the data is latched on the rising edge of CSB.

REGISTER READ-BACK

Not all registers can be read. Only the device ID (registers R0, R1 and R2) and the status

registers can be read. These status registers are labelled as “read only” in the Register Map

section.

The read-only status registers can be read back via the SDO pin. To enable readback the READEN

control register bit must be set. The status registers can then be read using one of two methods,

selected by the CONTREAD register bit.

Each time a read operation is performed after any write operation, the first read result may contain

corrupt data. To ensure correct operation, the first read result should be ignored and a second read

operation carried out. Subsequent register reads are unaffected until further register writes are

performed.

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PD Rev 4.3 August 2007

18

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