WM8772(2005) Просмотр технического описания (PDF) - Wolfson Microelectronics plc

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WM8772
(Rev.:2005)

24-bit, 192kHz 6-Channel Codec with Volume Control

Wolfson Microelectronics plc 

WM8772EDS – 28 LEAD SSOP

Production Data

DEVICE DESCRIPTION

INTRODUCTION

WM8772EDS is a complete 6-channel DAC, 2-channel ADC audio codec, including digital

interpolation and decimation filters, multi-bit sigma delta stereo ADC, and switched capacitor multi-

bit sigma delta DACs with digital volume controls on each channel and output smoothing filters.

The device is implemented as three separate stereo DACs and a stereo ADC in a single package

and controlled by a single interface.

Each stereo DAC has its own data input DIN1/2/3, the stereo ADC has it’s own data output DOUT.

The word clock LRC, bit clock BCLK and master clock MCLK are shared between them.

The Audio Interface may be configured to operate in either master or slave mode. In Slave mode

LRC and BCLK are all inputs. In Master mode LRC and BCLK are all outputs.

Each DAC has its own digital volume control that is adjustable in 0.5dB steps. The digital volume

controls may be operated independently. In addition, a zero cross detect circuit is provided for each

DAC for the digital volume controls. The digital volume control detects a transition through the zero

point before updating the volume. This minimises audible clicks and ‘zipper’ noise as the gain values

change.

Control of internal functionality of the device is by 3-wire serial or pin programmable control interface.

The software control interface may be asynchronous to the audio data interface as control data will

be re-synchronised to the audio processing internally.

Operation using master clocks of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided for the DAC,

for operation of both the ADC and DAC master clocks of 256fs, 384fs, 512fs and 768fs is provided.

In Slave mode selection between clock rates is automatically controlled. In master mode, the sample

rate is set by control bits RATE. Audio sample rates (fs) from less than 8ks/s up to 192ks/s are

allowed for the DAC and from less than 32ks/s up to 96ks/s for the ADC, provided the appropriate

master clock is input.

The audio data interface supports right, left and I2S interface formats along with a highly flexible DSP

serial port interface.

AUDIO DATA SAMPLING RATES

In a typical digital audio system there is only one central clock source producing a reference clock to

which all audio data processing is synchronised. This clock is often referred to as the audio system’s

Master Clock. The external master system clock can be applied directly through the MCLK input pin

with no software configuration necessary. In a system where there are a number of possible sources

for the reference clock it is recommended that the clock source with the lowest jitter be used to

optimise the performance of the ADC and DAC.

The master clock for WM8772EDS supports audio sampling rates from 128fs to 768fs, where fs is

the audio sampling frequency (LRC) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz (for DAC

operation only). For ADC operation sample rates from 256fs to 768fs are supported. The master

clock is used to operate the digital filters and the noise shaping circuits.

In Slave mode the WM8772EDS has a master clock detection circuit that automatically determines

the relationship between the system clock frequency and the sampling rate (to within +/- 32 master

clocks). If there is a greater than 32 clocks error the interface defaults to 768fs mode. The master

clocks must be synchronised with LRC, although the WM8772EDS is tolerant of phase variations or

jitter on this clock. Table 6 shows the typical master clock frequency inputs for the WM8772EDS.

The signal processing for the WM8772EDS typically operates at an oversampling rate of 128fs for

both ADC and DAC. The exception to this for the DAC is for operation with a 128/192fs system clock,

e.g. for 192kHz operation, when the oversampling rate is 64fs. For ADC operation at 96kHz it is

recommended that the user set the ADCOSR bit. This changes the ADC signal processing

oversample rate to 64fs.

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PD Rev 4.2 October 2005

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