WM8750L Просмотр технического описания (PDF) - Wolfson Microelectronics plc

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WM8750L

Stereo CODEC for Portable Audio Applications

Wolfson Microelectronics plc 

WM8750L

CONTROL INTERFACE TIMING – 3-WIRE MODE

CSB

tCSL

SCLK

tSCY

tSCH

tSCL

tSCS

tCSH

tCSS

Product Preview

SDIN

tDSU

tDHO

LSB

Figure 4 Control Interface Timing – 3-Wire Serial Control Mode

Test Conditions

DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless

otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Program Register Input Information

SCLK rising edge to CSB rising edge

tSCS

80

ns

SCLK pulse cycle time

tSCY

200

ns

SCLK pulse width low

tSCL

80

ns

SCLK pulse width high

tSCH

80

ns

SDIN to SCLK set-up time

tDSU

40

ns

SCLK to SDIN hold time

tDHO

40

ns

CSB pulse width low

tCSL

40

ns

CSB pulse width high

tCSH

40

ns

CSB rising to SCLK rising

tCSS

40

ns

Pulse width of spikes that will be suppressed

tps

5

ns

PP Rev 1.77 May 2003

14

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