WM8750CJLGEFL Просмотр технического описания (PDF) - Wolfson Microelectronics plc
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WM8750CJLGEFL Datasheet PDF : 61 Pages
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WM8750JL
CONTROL INTERFACE TIMING – 2-WIRE MODE
SDIN
SCLK
t3
t6
t1
t5
t2
t7
t9
t3
t4
Production Data
t8
Figure 5 Control Interface Timing – 2-Wire Serial Control Mode
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK Frequency
0
526
kHz
SCLK Low Pulse-Width
t1
1.3
us
SCLK High Pulse-Width
t2
600
ns
Hold Time (Start Condition)
t3
600
ns
Setup Time (Start Condition)
t4
600
ns
Data Setup Time
t5
100
ns
SDIN, SCLK Rise Time
t6
300
ns
SDIN, SCLK Fall Time
t7
300
ns
Setup Time (Stop Condition)
Data Hold Time
t8
600
t9
ns
900
ns
Pulse width of spikes that will be suppressed
tps
0
5
ns
w
PD, April 2012, Rev 4.1
14
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