W77E516 Просмотр технического описания (PDF) - Winbond
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W77E516 Datasheet PDF : 85 Pages
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Preliminary W77E516
SM0_1/FE_1: Serial port 1, Mode 0 bit or Framing Error Flag 1: The SMOD0 bit in PCON SFR
determines whether this bit acts as SM0_1 or as FE_1, the operation of SM0_1 is
described below. When used as FE_1, this bit will be set to indicate an invalid stop
bit. This bit must be manually cleared in software to clear the FE_1 condition.
SM1_1: Serial port 1 Mode bit 1:
SM0_1 SM1_1
0
0
0
1
1
0
1
1
Mode
0
1
2
3
Description
Synchronous
Asynchronous
Asynchronous
Asynchronous
Length
8
10
11
11
Baud rate
4/12 Tclk
variable
64/32 Tclk
variable
SM2_1: Multiple processors communication. Setting this bit to 1 enables the multiprocessor
communication feature in mode 2 and 3. In mode 2 or 3, if SM2_1 is set to 1, then RI_1
will not be activated if the received 9th data bit (RB8_1) is 0. In mode 1, if SM2_1 = 1, then
RI_1 will not be activated if a valid stop bit was not received. In mode 0, the SM2_1 bit
controls the serial port 1 clock. If set to 0, then the serial port 1 runs at a divide by 12 clock
of the oscillator. This gives compatibility with the standard 8052. When set to 1, the serial
clock become divide by 4 of the oscillator clock. This results in faster synchronous serial
communication.
REN_1: Receive enable: When set to 1 serial reception is enabled, otherwise reception is disabled.
TB8_1: This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared by software
as desired.
RB8_1: In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2_1 = 0, RB8_1 is the
stop bit that was received. In mode 0 it has no function.
TI_1: Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or
at the beginning of the stop bit in all other modes during serial transmission. This bit must be
cleared by software.
RI_1: Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or
halfway through the stop bits time in the other modes during serial reception. However the
restrictions of SM2_1 apply to this bit. This bit can be cleared only by software.
Serial Data Buffer 1
Bit:
7
6
5
4
3
2
1
0
SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0
Mnemonic: SBUF1
Address: C1h
SBUF1.7 − 0: Serial data of the serial port 1 is read from or written to this location. It actually
consists of two separate 8-bit registers. One is the receive resister, and the other is
the transmit buffer. Any read access gets data from the receive data buffer, while
write accesses are to the transmit data buffer.
WSCON
Bit:
7
6
5
4
3
2
1
0
WS
-
-
-
-
-
-
-
Mnemonic: WSCON
Address: C2h
- 25 -
Publication Release Date: August 16, 2002
Revision A1
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