W742C814
WDTR.0 will be set to one when WDT time out and can be reset to zero by:
POWER ON RESET, RESET PIN, CLR WDT
Table 2. The bit 1 of WatchDog Timer Register (WDTR) reset item
RESET ITEM
Program Counter (PC)
WDTR.1 = 1
0000H
Stack Pointer (SP)
ROMPR, PAGE, DBKR, WRP, ACC, CF, ZF, SCR
Registers
IEF, HEF, SEF, HCF, PEF, EVF Flags
DIV0, DIV1
TM0, TM1, MR0, MR1 Registers
-
-
IEF = Reset
-
-
Timer 0 Input Clock
-
Timer 1 Input Clock
-
MFP Output
-
PM0 Register
-
PM1, PM2, PM5 Registers
-
PSR0 Register
-
Input/Output Orts RA, RB, RD
-
Output Ports RE
-
RA, RB Ports Output Type
-
RC Port Pull-high Resistors
-
Input Clock of the Watchdog Timer
-
DTMF Output
-
BUZCR Register
-
FLCD
-
LCD Display
-
LCDR
-
Segment Output Mode
-
-: keep the status
Note: SCR.2 is reserved
WDTR.1 = 0
0000H
Reset
Reset
Reset
Reset
Reset
FOSC/4
FOSC
Low
Reset
Set (1111B)
Reset
Input mode
High
CMOS type
Disable
FOSC/2048
Hi-Z
Reset
Q5 to Q9 Reset
OFF
Reset
LCD drive output
6.11 Timer/Counter
6.11.1 Timer 0 (TM0)
Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into
TM0 by executing the MOV TM0L(TM0H),R instructions. When the MOV TM0L(TM0H),R instructions
are executed, it will stop the TM0 down-counting (if the TM0 is down-counting) and reset the MR0.3 to
- 15 -
Publication Release Date: February 12, 2003
Revision A2