25Q32VFIG Просмотр технического описания (PDF) - Winbond

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25Q32VFIG

32M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

Winbond 

W25Q32V

10.2.6 Read Status Register-1 (05h) and Read Status Register-2 (35h)

The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is

entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 and “35h” for

Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on

the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in figure 6. The Status

Register bits are shown in figure 3a and 3b and include the BUSY, WEL, BP2-BP0, TB, SEC, SRP0,

SRP1, QE and SUS bits (see description of the Status Register earlier in this datasheet).

The Read Status Register instruction may be used at any time, even while a Program, Erase or Write

Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when

the cycle is complete and if the device can accept another instruction. The Status Register can be read

continuously, as shown in Figure 6. The instruction is completed by driving /CS high.

Figure 6. Read Status Register Instruction Sequence Diagram

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