VDP3108 Просмотр технического описания (PDF) - Micronas

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VDP3108

Single-Chip Video Processor

Micronas 

ADVANCE INFORMATION

VDP 3108

2.6.2. Deflection Processing

The deflection processing generates the signals for the

horizontal and vertical drive (fig. 2–27). This block con-

tains two phase-locked loops:

– PLL2 generates the horizontal and vertical timing.

Phase and frequency are synchronized by the front

sync signal. The Main Sync (MSY) signal that is gener-

ated from PLL2 is a multiplex of all display related data

(fig. 2–28). This signal is intended for use by other pro-

cessors, e.g. a PIP processor can use this signal to ad-

just to a certain display position.

– PLL3 adjusts the phase of the horizontal drive pulse

and compensates for the delay of the horizontal output

stage.

The horizontal drive circuitry uses a digital sine wave

generator to produce the exact (subclock) timing for the

drive pulse. The generator runs at 1 MHz; in the output

stage the frequency is divided down to give drive-pulse

period and width. In standby mode, the output stage is

driven from an internal 1 MHz clock that is derived from

the 20 MHz main clock oscillator and a fixed drive pulse

width is used. When the circuit is switched out of standby

operation the drive pulse width is programmable. The

horizontal drive uses a high voltage (8V) open drain out-

put transistor.

phase

comparator

&

lowpass

DCO

PLL3

sinewave

generator

DAC

&

LPF

1:64

&

output

stage

H

flyback

H

drive

Standby clock

FSY

main

sync

interface

phase

comparator

&

lowpass

DCO

line

counter

composite

sync

generator

CSY

MSY

main

sync

generator

VDATA

vertical

serial

data

display

timing

PLL2

blanking, clamping, etc.

clock & control

E/W

correction

PWM

15 bit

sawtooth

PWM

15 bit

V

flyback

E/W

ouput

V

output

Fig. 2–27: Deflection processing block diagram

input

analog

video

MSY M1 M2

(not in scale)

timing reference for PICTURE bus

– chroma multiplex sync

– active picture data after xxx clocks

Fig. 2–28: Main sync format

MICRONAS INTERMETALL

M1

line

[0]

line

[7]

Parity

M2

line not not not not not

[8] used used used used used

F

V Parity

V: Vert. blanking

0 = off

1 = on

F: Field #

0 = Field 1

1 = Field 2

line: Field line #

1...N

21

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