UPD75236GJ Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPD75236GJ Datasheet PDF : 190 Pages
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µPD75236
(2) Serial transfer operation
(a) 2-wire and 3-wire serial I/O mode (SCK...Internal clock output)
PARAMETER
SCK cycle time
SCK high and low level
widths
SI setup time (to SCK↑)
SI hold time (from SCK↑)
SO output delay time
from SCK↓
SYMBOL
tKCY1
tKL1
tKH1
tSIK1
tKSI1
tKSO1
TEST CONDITIONS
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
RL = 1 k Ω
CL = 100 pF*
VDD = 4.5 to 6.0 V
MIN. TYP.
1600
3800
(tKCY/2)-50
(tKCY/2-150)
150
400
MAX. UNIT
ns
ns
ns
ns
ns
ns
250
ns
1000
ns
* RL and CL are SO output line load resistance and load capacitance, respectively.
(b) 2-wire and 3-wire serial I/O mode (SCK...External clock input)
PARAMETER
SCK cycle time
SYMBOL
tKCY2
TEST CONDITIONS
VDD = 4.5 to 6.0 V
SCK high and low level
widths
SI setup time (to SCK↑)
SI hold time (from SCK↑)
SO output delay time
from SCK↓
tKL2
tKH2
tSIK2
tKSI2
tKSO2
VDD = 4.5 to 6.0 V
RL = 1 k Ω
CL = 100 pF*
VDD = 4.5 to 6.0 V
MIN.
800
3200
400
1600
100
400
TYP. MAX. UNIT
ns
ns
ns
ns
ns
ns
300
ns
1000
ns
* RL and CL are SO output line load resistance and load capacitance, respectively.
176
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