UPD4721GS-GJG Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPD4721GS-GJG Datasheet PDF : 16 Pages
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BLOCK DIAGRAM/PIN CONFIGURATION (Top View)
µPD4721
+3.3 V
or
+5 V
C1 +
+10 V
C3 +
1 VDD
2 C1+
3 VCC
C5 +
4 C1–
5 C5+
6 C5–
DIN1 7
Note 4
DIN2 8
C4+ 20
GND 19
C4– 18
+
C4
+
C2
VSS 17
16 STBY
–10 V
300 Ω
300 Ω
15 VCHA
14 DOUT1
13 DOUT2
ROUT1 9
ROUT2 10
5.5 kΩ
5.5 kΩ
12 RIN1
11 RIN2
Note 1. VDD and VSS are output pins stepped up internally. These pins should not be loaded directly.
2. Capacitors C1 to C5 with a breakdown voltage of 20 V or higher are recommended. And it is
recommended to insert the capacitor that is 0.1 µF to 1 µF between VCC and GND.
3. If VCHA is kept low level (in 5 V mode), capacitor C5 is not necessary.
4. The pull-up resistors at driver input are active resistors.
2
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