UPD161831 Просмотр технического описания (PDF) - NEC => Renesas Technology

Номер в каталоге

Компоненты Описание

производитель

UPD161831

240/244-OUTPUT TFT-LCD SOURCE DRIVER WITH TIMING GENERATOR (COMPATIBLE WITH 64-GRAY SCALES)

NEC => Renesas Technology 

µPD161831

4.2.3 Horizontal period valid input start timing setting register

This register sets the timing to start inputting the valid data of the horizontal period in HSYNC and VSYNC mode.

It sets the number of dot clocks from the falling edge of the HSYNC signal until the input data becomes valid. If

transferring display data twice is selected, set half the number of dot clocks actually needed. Note also that the

setting of this register is reflected from the operation of the next frame after the register is set.

Table 4−5. Horizontal Period Valid Input Start Timing Setting Register (R1)

Register Set Value

00H

01H

:

04H

05H

06H

07H

:

FDH

FEH

FFH

Number of Dot Clocks

4 clocks

4 clocks

:

4 clocks

5 clocks

6 clocks

7 clocks

:

253 clocks

254 clocks

255 clocks

4.2.4 Vertical period valid input start timing setting register

This register sets the timing to start inputting the valid data of the vertical period in HSYNC and VSYNC mode.

It sets the number of HSYNC from the falling edge of the VSYNC signal until the input data becomes valid. Note

also that the setting of this register is reflected from the operation of the next frame after the register is set.

Table 4−6. Vertical Period Valid Input Start Timing Setting Register (R2)

Register Set Value

00H

01H

02H

03H

04H

05H

06H

:

FDH

FEH

FFH

Number of HSYNC Signals

2

2

2

3

4

5

6

:

253

254

255

18

Preliminary Product Information S16269EJ2V0PM

Share Link: