UPD161831 Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPD161831
NEC => Renesas Technology
UPD161831 Datasheet PDF : 67 Pages
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µPD161831
Table 4−2. Command Register List (2/2)
Register
D5 to D0
No.
D5 D4 D3 D2 D1 D0
Register Name
Default
Value
R36
1 0 0 1 0 0 RSW_O start timing setting
0FH
R37
1 0 0 1 0 1 RSW_O end timing setting
1DH
R38
1 0 0 1 1 0 GSW_O start timing setting
1EH
R39
1 0 0 1 1 1 GSW_O end timing setting
2CH
R40
1 0 1 0 0 0 BSW_O start timing setting
2DH
R41
1 0 1 0 0 1 BSW_O end timing setting
3BH
R42
1 0 1 0 1 0 EXT1_O start timing setting
0AH
R43
1 0 1 0 1 1 EXT1_O end timing setting
0AH
R44
1 0 1 1 0 0 EXT2_O start timing setting
0AH
R45
1 0 1 1 0 1 EXT2_O end timing setting
0AH
R46
1 0 1 1 1 0 EXT3_O start timing setting
0AH
R47
1 0 1 1 1 1 EXT3_O end timing setting
0AH
R48
1 1 0 0 0 0 EXT1 to EXT3 function setting
80H
R49
1 1 0 0 0 1 GOE1 start timing setting
04H
R50
1 1 0 0 1 0 GOE1 end timing setting
38H
R51
1 1 0 0 1 1 Dummy line setting
00H
R52, R53 − − − − − − Use prohibited (Not used)
−
R54
1 1 0 1 1 0 COM2, VCLAMP control
00H
R55
1 1 0 1 1 1 Test mode setting
00H
R56 to R255 − − − − − − Use prohibited (Not used)
−
Remarks 1. O: Enabled, -: Disabled, ∆1: Only bit 3 disabled, ∆2: Only bit 7 enabled
2. The internal set timing is the timing at which the command is enabled.
C: Enabled when command is set
F: Enabled at beginning of frame
L: Enabled at beginning of line
Timing Generator
Function
Reset
Use Not used Command Hard
O
−
O
−
O
−
O
−
O
−
O
−
O
−
O
−
O
−
O
−
O
−
O
−
O
−
O
−
O
−
O
−
O
−
O
−
O
−
O
−
O
−
O
−
O
−
O
−
O
∆2
O
−
O
−
O
−
O
−
O
−
O
−
O
−
−
−
−
−
O
O
O
O
O
O
O
−
−
−
−
−
Internal Set
Timing
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
F
−
C
C
−
Notes 1. Bit 0 is enabled when line is set. Bit 3 is enabled when frame is set. Al other bits are enabled when command is set.
2. Bits 4 and 5 are enabled when hard reset is performed. All other bits are disabled.
16
Preliminary Product Information S16269EJ2V0PM
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