UPD16772 Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPD16772 Datasheet PDF : 20 Pages
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µPD16772
5 Timing Requirements (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Clock Pulse Width
PWCLK
VDD1 = 2.3 to 3.6 V
22
Clock Pulse High Period
PWCLK(H)
4
Clock Pulse Low Period
PWCLK(L) VDD1 = 2.3 to 3.0 V
7
VDD1 = 3.0 to 3.6 V
4
Data Setup Time
tSETUP1
3
Data Hold Time
tHOLD1
0
Start Pulse Setup Time
tSETUP2
3
Start Pulse Hold Time
tHOLD2
0
POL21/22 Setup Time
tSETUP3
3
POL21/22 Hold Time
tHOLD3
VDD1 = 2.3 to 3.0 V
1
VDD1 = 3.0 to 3.6 V
0
Start Pulse Low Period
tSPL
1
STB Pulse Width
PWSTB
2
Last Data Timing
tLDT
2
CLK-STB Time
tCLK-STB
CLK ↑ → STB ↑
6
STB-CLK Time
tSTB-CLK
STB ↑ → CLK ↑
14
VDD1 = 2.3 to 3.0 V
STB ↑ → CLK ↑
6
VDD1 = 3.0 to 3.6 V
Time Between STB and Start Pulse tSTB-STH
STB ↑ → STHR(STHL) ↑
2
POL-STB Time
tPOL-STB
POL ↑ or ↓ → STB ↑
–5
STB-POL Time
tSTB-POL
STB ↓ → POL ↓ or ↑
6
Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CLK
CLK
ns
ns
ns
CLK
ns
ns
14
Data Sheet S14416EJ1V0DS00
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