UPD16707 Просмотр технического описания (PDF) - NEC => Renesas Technology

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производитель

UPD16707

263/256-OUTPUT TFT-LCD GATE DRIVER

NEC => Renesas Technology 

µ PD16707

3. PIN FUNCTIONS

Pin Symbol

Pin Name

I/O

Description

O1 to O263

O0, O264

R,/LR,

R,/LL

Driver output

Driver output

Output

Output

These pins output scan signals that drive the vertical direction (gate lines) of a TFT-

LCD. The output signals change in synchronization with the rising edge of shift clock

CLK. The driver output amplitude is VDD2 to VEE.

The signal of VEE level is outputted by fixation.

Shift direction control Input The shift direction control pin of shift register. The shift directions of shift register are

as follows.

R,/LR, R,/LL = H : right shift : STVR → O1 → O263 → STVL

R,/LR, R,/LL = L : left shift : STVL → O263 → O1 → STVR

R,/LR and R,/LL are connected inside IC.

STVR,

STVL

Start pulse

input/output

CLKR,

CLKL

Shift clock input

OER,OEL Output enable input

/AOR, /AOL All-on control

MODE

Selection of Number

of outputs

PASSR,

PASSL

VDD1

Pass line

Logic power supply

I/O

Input

Input

Input

Input

Input

This is the I/O of the internal shift register. The start pulse is read at the rising edge of

shift clock CLK (CLKR,CLKL), and scan signals are output from the driver output pins.

The input level is a VDD1 to VSS (logic level). When in MODE = H, the start pulse is

output at the falling edge of the 263rd clock of shift clock CLK, and is cleared at the

falling edge of the 264th clock.

The output level is VDD1 to VSS (logic level).

This pin inputs a shift clock to the internal shift register. The shift operation is

performed in synchronization with the rising edge of this input. CLKR and CLKL are

connected inside IC.

When this pin goes high level, the driver output is fixed to VEE level.

The shift register is not cleared. CLK is asynchronous in the clock.

OER and OEL are connected inside IC.

When this pin goes low level, all driver output = VDD2 level.

The shift register is not cleared. This pin has priority over OER,OEL.

This pin is pulled up to VDD1 power supply inside IC.

CLK is asynchronous in the clock.

/AOR and /AOL are connected inside IC.

MODE = V DD1 or open: 263 outputs

MODE = VSS: 256 outputs (Driver pins O129 to O135 are invalid.)

Input level is VDD1 to VSS (logic level)

This pin is pulled up to VDD1 power supply inside IC.

PASSR and PASSL are connected inside IC.

– 2.3 to 3.6 V

VDD2

Driver positive power – 15 to 25 V. The driver output: high level

supply

VSS

Logic ground

– Connect this pin to the ground of the system.

VEE

Negative Power

supply for internal

operation

DUMMY Note Dummy

– −15 to −5 V. The driver output: low level

– No dummy pins are connected with other pins inside IC.

Note DUMMY pins are adapted only for chip product. (There is no DUMMY pin in TCP product.)

Cautions 1. To prevent latch-up, turn on power to VDD1 → logic input → VEE → VDD2 in this order. Turn off power

in the reverse order. These power up/down sequence must be observed also during

transition period.

2. Insert a capacitor of about 0.1 µF between each power line, as shown below, to secure noise

margin such as VIH and VIL.

VDD2

VDD1

VSS

VEE

0.1 µF

0.1 µF

0.1 µF

12

Data Sheet S16411EJ1V0DS

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