UPD16647 Просмотр технического описания (PDF) - NEC => Renesas Technology
Номер в каталоге
Компоненты Описание
производитель
UPD16647 Datasheet PDF : 16 Pages
| |||
µ PD16647
Switching Characteristics (TA = −10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VDD2 = 5.0 V ± 0.5 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Start Pulse Delay Time tPLH1
CL = 15 pF
7
12
ns
tPHL1
7
12
ns
Driver Output Delay Time tPLH2
tPLH3
tPHL2
tPHL3
VDD2 = 5.0 V
5 kΩ +36 pF
VO: 0.1 V → 4.9 V
VO: 4.9 V → 0.1 V
2.2
10
µs
2.9
12
µs
2.6
10
µs
3.6
12
µs
Input Capacitance
CI1
STHR (STHL), TA = 25 °C
CI2
V0 to V9, TA = 25 °C
CI3
STHR (STHL), other than V0 to V9 , TA = 25 °C
10
20
pF
100
150
pF
10
15
pF
<Output Load>
Output
2.5 kΩ
2.5 kΩ
9 pF
18 pF
9 pF
Timing Requirements (TA = −10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VDD2 = 5.0 V ± 0.5 V, VSS1 = VSS2 = 0 V)
Parameter
Clock Pulse Width
Clock Low Period
Clock High Period
Data Setup Time
Data Hold Time
Start Pulse Setup Time
Start Pulse Hold Time
INV Setup Time
INV Hold Time
Start Pulse Low Period
Start Pulse Rise Time
STB Setup Time
5 STB Pulse Width
Data Invalid Period
Last Data Timing
CLK-STB Time
STB-CLK Time
Symbol
Condition
PWCLK
PWCLK (L)
PWCLK (H)
tSETUP1
tHOLD1
tSETUP2
tHOLD2
tSETUP4
tHOLD4
tSPL
tSPR
tSETUP3
PWSTB
tINV
384 outputs
402 outputs
tLDT
tCLK-STB
tSTB-CLK
CLK ↑ → STB ↑
STB ↑ → CLK ↑
MIN.
TYP.
MAX.
Unit
20
ns
4
ns
4
ns
4
ns
0
ns
4
ns
0
ns
4
ns
0
ns
2
CLK
128
CLK
134
CLK
1
CLK
2
CLK
1
CLK
1
CLK
7
ns
7
ns
12
Data Sheet S13607EJ2V0DS00
Share Link: 