UPD16634A Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPD16634A Datasheet PDF : 20 Pages
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µPD16634A
Timing Requirements (TA = −10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VSS1 = VSS2 = 0 V, tr = tf = 8.0 ns)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Clock pulse width
PWCLK
25
Clock pulse low period
PWCLK (L)
6
Clock pulse high period
PWCLK (H)
6
Data setup time
tSETUP1
6
Data hold time
tHOLD1
6
Start pulse setup time
tSETUP2
5
Start pulse hold time
tHOLD2
5
Start pulse low period
tSPL
6
POL2 setup time
tSETUP3
6
POL2 hold time
tHOLD3
6
STB pulse width
PWSTB
1
Data invalid period
tINV
1
Final data timing
tLDT
2
5 CLK-STB time
tCLK-STB
CLK↑→STB↑
6
5 STB-CLK time
tSTB-CLK
STB↑ →CLK↑
6
Time between STB and start pulse tSTB-STH STB↓ →CLK↑
60
POL-STB time
tPOL-STB
POL↑or↓ →STB↑
−5
STB-POL time
tSTB-POL
STB↓ →POL↑ or↓
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
CLK
CLK
ns
ns
ns
ns
ns
14
Data Sheet S12595EJ2V0DS00
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