UPD16635 Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPD16635 Datasheet PDF : 19 Pages
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µPD16635
Electrical Specifications (TA = –10 to +75 °C, VDD1 = 3.3 V ±0.3 V, VDD2 = 13.0 V ±0.5 V, VSS1 = VSS2 = 0 V)
Parameter
Output Voltage DeviationNote 1
Average Output Voltage
VariationNote 2
Output Voltage Range
Logic Part Dynamic Current
Consumption
Driver Part Dynamic Current
Consumption
Symbol
∆VO
∆VAV
VO
IDD1
IDD2
Condition
Input data: 00H to 3FH
Input data: 00H to 3FH
Input data: 00H to 3FH
VDD1; when with no loadNotes 3, 4
VDD2; when with no loadNotes 3, 4
MIN. TYP. MAX. Unit
±5
±20
mV
±10
mV
0.2
VDD2 – 0.2
V
1.0
6.0
mA
3.5
9.0
mA
Notes 1. The output voltage deviation refers to the voltage difference between adjoining output pins when the
display data is the same (within the chip).
2. The average output voltage variation refers to the average output voltage difference between chips.
The average output voltage refers to the average voltage between chips when the display data is the
same.
3. The STB cycle is defined to be 30 µs at fCLK = 25 MHz.
The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured
values in the dot checkerboard input pattern.
4. Refers to the current consumption per driver when cascades are connected under the assumption of
SVGA single-sided mounting (10 units).
Switching Characteristics (TA = –10 to +75 °C, VDD1 = 3.3 V ±0.3 V, VDD2 = 13.0 V ±0.5 V, VSS1 = VSS2 = 0 V)
Parameter
Start Pulse Delay Time
Driver Output Delay Time 1
Driver Output Delay Time 2
Driver Output Delay Time 3
Driver Output Delay Time 4
Input Capacitance 1
Input Capacitance 2
Symbol
tPLH1
tPHL2
tPHL3
tPLH2
tPLH3
C1
C2
Condition
CL = 25 pF
CL = 50 pF, R = 50 kΩ
CL = 50 pF, R = 50 kΩ
CL = 50 pF, R = 50 kΩ
CL = 50 pF, R = 50 kΩ
STHR, STHL excluded
TA = 25 °C
STHR, STHL
TA = 25 °C
MIN. TYP. MAX. Unit
10
15
ns
7
11
µs
13
17
µs
7
11
µs
13
17
µs
5
15
pF
5
15
pF
12
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