UPD16448A Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPD16448A
NEC => Renesas Technology
UPD16448A Datasheet PDF : 24 Pages
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µPD16448A
SWITCHING CHARACTERISTICS (TA = -30 to +85 °C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 ±0.5 V, VSS1 = VSS2 = 0 V)
Parameter
Start pulse propagation delay time
Maximum clock frequency 1
Maximum clock frequency 2
Logic input capacitance
STHL, STHR input capacitance
Video input capacitance
Symbol
tPHL
tPLH
fmax. 1
fmax. 2
CI1
CI2
C3
Condition
CL = 20 pF
CL = 20 pF
With 3-phase clock input
Other than STHL, STHR
STHL, STHR
C1 to C3, VVI = 2.0 V
MIN.
10
10
15
8
TYP.
MAX.
54
54
15
20
50
Unit
ns
ns
MHz
MHz
pF
pF
pF
TIMING REQUIREMENTS (TA = -30 to +85 °C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 ± 0.5 V, VSS1 = VSS2 = 0 V)
Parameter
Clock pulse width
Start pulse setup time
Start pulse hold time
Reset pulse width
INH setup time
INH hold time
Reset-INH time
INH pulse width
Symbol
PWCLI
tSETUP
tHOLD
PWRES
tISETUP
tIHOLD
tR-I
PWINH
Condition
Duty = 50 %
MIN.
33
8
8
66
33
33
81
5
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
CLK
Remark Keep the rise and fall times of the logic input signals to within tr = tf = 5 ns (10 to 90%).
As an example, the switching characteristic wave of CLI1 is defined on the next page.
19
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