UPD160040 Просмотр технического описания (PDF) - NEC => Renesas Technology
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производитель
UPD160040
NEC => Renesas Technology
UPD160040 Datasheet PDF : 19 Pages
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µPD160040
Timing Requirements (TA = −10 to +75°C, VDD1 = 2.5 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns)
Parameter
Symbol
Condition
MIN.
TYP.
Clock pulse width
PWCLK
3.0 V ≤ VDD1 ≤ 3.6 V
18
2.5 V ≤ VDD1 < 3.0 V
25
Clock pulse high period
PWCLK (H) 3.0 V ≤ VDD1 ≤ 3.6 V
4
2.5 V ≤ VDD1 < 3.0 V
6
Clock pulse low period
PWCLK (L)
4
Data setup time
tSETUP1
0
Data hold time
tHOLD1
4
Start pulse setup time
tSETUP2
0
Start pulse hold time
tHOLD2
4
POL21, POL22 setup time
tSETUP3
0
POL21, POL22 hold time
tHOLD3
4
STB pulse width
PWSTB
1.0
Last data timing
tLDT
2
CLK-STB time
tCLK-STB
CLK ↑→ STB↑
4
STB-CLK time
tSTB-CLK
STB ↑→ CLK↑
4
Time between STB and start pulse tSTB-STH STB ↑→ STHR (STHL) ↑
2
POL-STB time
tPOL-STB
POL ↑ or ↓→ STB ↑
4
STB-POL time
tSTB-POL
STB ↓→ POL ↓ or ↑
4
STB-SRC time
t STB-SRC STB ↑ → SRC ↑
0
STB-ORC time
tSTB-ORC
STB ↓→ ORC ↑
0
Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
CLK
ns
ns
CLK
ns
ns
ns
ns
Data Sheet S15859EJ1V0DS
15
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