UPB1009K-E1 Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPB1009K-E1

NEC’s LOW POWER GPS RF RECEIVER BIPOLAR ANALOG + INTEGRATED CIRCUIT

NEC => Renesas Technology 

UPB1009K

As illustrated in the operation timing chart below, the data of SampleN is pipeline delayed by 1.5 clocks during

normal operation, and is output at the rising edge of the sample clock with output delay time Tod. When the

operation is changed from normal operation to power-down operation, the status of the output data

immediately before the power-down operation is retained (drive status).

(a) Normal Operation

2ndIFin

SCKin

SampleN

SampleN+1 SampleN+2

SampleN+3

SampleN+4

SampleN+5

Tclk

Tds

Tch

Tcl

Tpld

Tds

Toh

D0-D3

N-2

N-1

N

N+1

N+2

N+3

: Analog signal sampling timing

The following table shows each timing parameter for reference purposes.

Symbol

Parameter

Tod Output Delay

Tpld Pipeline Delay

Tds Sampling Delay

(Aperture Delay)

Toh Output Hold Time

Test Conditions

CL = 10 pF, fclk = 19.2 MHz

MIN.

−

−

−

TYP.

−

1.5

2

MAX.

12

−

−

Unit

ns

clock

ns

2

−

−

ns

15

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