UPA1774 Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPA1774 Datasheet PDF : 8 Pages
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µPA1774
ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate Cut-off Voltage
IDSS
IGSS
VGS(off)
VDS = −60 V, VGS = 0 V
VGS = m16 V, VDS = 0 V
VDS = −10 V, ID = 1 mA
−10 µA
m10 µA
−1.5 −2.0 −2.5 V
Forward Transfer Admittance
| yfs | VDS = −10 V, ID = −2.0 A
2.5 4.3
S
Drain to Source On-state Resistance
RDS(on)1 VGS = −10 V, ID = −2.0 A
200 250 mΩ
RDS(on)2 VGS = −4.5 V, ID = −2.0 A
230 300 mΩ
RDS(on)3 VGS = −4.0 V, ID = −2.0 A
240 330 mΩ
Input Capacitance
Ciss
VDS = −10 V
420
pF
Output Capacitance
Coss
VGS = 0 V
80
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
30
pF
Turn-on Delay Time
td(on)
VDD = −30 V, ID = −2.0 A
8
ns
Rise Time
tr
VGS = −10 V
5
ns
Turn-off Delay Time
td(off)
RG = 0 Ω
35
ns
Fall Time
tf
8
ns
Total Gate Charge
QG
VDD = −48 V
10
nC
Gate to Source Charge
QGS
VGS = −10 V
1.7
nC
Gate to Drain Charge
QGD ID = −2.8 A
2.2
nC
Body Diode Forward Voltage
VF(S-D) IF = 2.8 A, VGS = 0 V
0.89
V
Reverse Recovery Time
trr
IF = 2.8 A, VGS = 0 V
45
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A/µs
65
µC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG
50 Ω
VDD
VGS = –20 → 0 V
−
IAS BVDSS
VDS
ID
VDD
Starting Tch
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS (−)
0
τ
τ = 1 µs
Duty Cycle ≤ 1%
RL
VDD
VGS (−)
VGS
Wave Form
0 10%
VDS (−)
90%
VDS
VDS
0
Wave Form
td(on)
VGS 90%
10% 10%
90%
tr td(off) tf
ton
toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = −2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet G15380EJ2V0DS
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