UDA1340M Просмотр технического описания (PDF) - Philips Electronics
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UDA1340M Datasheet PDF : 24 Pages
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Philips Semiconductors
Low-voltage low-power stereo audio
CODEC with DSP features
Preliminary specification
UDA1340
AC CHARACTERISTICS (DIGITAL)
VDDD = VDDA = VDDO = 2.7 to 3.6 V; Tamb = −20 to +85 °C; RL = 5 kΩ; all voltages referenced to ground
(pins 1, 11, 22 and 27); unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
Tcy
tCWL
tCWH
clock cycle
fsys LOW level pulse width
fsys HIGH level pulse width
fsys = 256fs
78
fsys = 384fs
52
fsys = 512fs
39
fsys < 19.2 MHz
30
fsys ≥ 19.2 MHz
40
fsys < 19.2 MHz
30
fsys ≥ 19.2 MHz
40
Serial input/output data timing; see Fig.7
tBCK
tBCK(H)
tBCK(L)
tr
tf
ts;DATI
th;DATI
td(DATO)(BCK)
td(DATO)(WS)
th;DATO
ts;WS
th;WS
bit clock period
bit clock HIGH time
bit clock LOW time
rise time
fall time
data input set-up time
data input hold time
data output delay time (from BCK falling edge)
data output delay time (from WS edge)
MSB-justified format
data output hold time
word selection set-up time
word selection hold time
1⁄64fs
100
100
−
−
20
0
−
−
0
20
10
Address and data transfer mode timing; see Figs 4 and 5
Tcy
tHC
tLC
ts;MA
th;MA
ts;MT
th;MT
ts;DAT
L3CLK cycle time
L3CLK HIGH period
L3CLK LOW period
L3MODE set-up time
L3MODE hold time
L3MODE set-up time
L3MODE hold time
L3DATA set-up time
500
250
250
address mode
190
address mode
190
data transfer mode 190
data transfer mode 190
data transfer mode 190
and address mode
th;DAT
L3DATA hold time
data transfer mode 30
and address mode
thalt
L3MODE halt time
190
TYP.
88
59
44
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
MAX. UNIT
131 ns
87
ns
66
ns
70
%Tsys
60
%Tsys
70
%Tsys
60
%Tsys
−
ns
−
ns
−
ns
20
ns
20
ns
−
ns
−
ns
80
ns
80
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
1997 Jul 09
17
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