UB084S01 Просмотр технического описания (PDF) - Unspecified
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UB084S01 Datasheet PDF : 19 Pages
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SPEC NO. : 413-212-061
PA G E
: 7/14
c. Input signal timing
Timing diagrams of input signal are shown in Fig 2.
(1). Timing characteristics of input signals
DE mode
Item
Clock frequency
Symbol
Fck
Horizontal blanking
Thb1
Horizontal display period Thd
Horizontal sync. period
Th
Vertical blanking
Tvb1
Vertical display width
Tvd
Vertical sync. period
Tv
(2). The timing condition of LVDS
Min.
38
235
-
1035
10
-
610
Typ.
40
256
800
1056
28
600
628
Item
Symbol Min.
Typ.
The differential level
VID
0.1
-
"
"
The common mode input
voltage
VIC
$
$
VID
2
-
The input setup time
tsu1
0.5
-
The input hold time
th1
0.5
-
Max.
42
500
-
1300
150
-
750
Unit
MHz
Clk
Clk
Clk
Th
Th
Th
Max.
0.6
2.4
#
$
$
VID
2
-
-
VID
VID = VIAP - VIAM
Remark
Unit
V
V
ns
ns
VIAP
VIAM
An
7 LCK
%
d. Display position
D( 1,1 )
D( 2,1 )
D( 1,2 )
...
D( 2,2 )
D( 1,Y )
...
D( 2,Y )
D( 1,599 ) D( 2,599 )
D( 1,600 ) D( 2,600 )
tsu1 th1
……
……
……
……
……
……
……
D( X,1 )
D( X,2 )
...
D( X,Y )
...
D( X,599 )
D( X,600 )
……
……
……
……
……
……
……
D( 799,1 ) D( 800,1 )
D( 799,2 )
...
D( 800,2 )
...
D( 799,Y )
...
D( 800,Y )
...
D( 799,599) D( 800,599 )
D( 799,600) D( 800,600)
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