UAA3580HN Просмотр технического описания (PDF) - Philips Electronics

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производитель

UAA3580HN

Wideband code division multiple access frequency division duplex zero IF receiver

Philips Electronics 

Philips Semiconductors

Wideband code division multiple access

frequency division duplex zero IF receiver

Objective specification

UAA3580

10 PROGRAMMING

10.1 Serial programming bus

A simple 3-wire unidirectional serial bus is used to program

the circuit. The 3 lines are DATA, CLK and EN.

The data sent to the device is loaded in bursts framed

by EN. Programming clock edges are ignored until EN

goes active LOW. The programmed information is loaded

into the addressed latch when EN goes HIGH (inactive).

This is allowed when CLK is in either state without causing

any consequences to the data register. Only the last

21 bits serially clocked into the device are retained within

the programming register. Additional leading bits are

ignored, and no check is made on the number of clock

pulses.

The fully static CMOS design uses virtually no current

when the bus is inactive. It can always capture new

programming data even during Power-down of the

synthesizer.

10.2 Data format

Data is entered with the most significant bit first. The

leading bits make up the data field, while the trailing four

bits are an address field. The address bits are decoded on

the rising edge of EN. This produces an internal load pulse

to store the data in the address latch.

To ensure that data is correctly loaded on first power-up,

EN should be held LOW and only taken HIGH after having

programmed an appropriate register. To avoid erroneous

divider ratios, the pulse is inhibited during the period when

data is read by the frequency dividers. This condition is

guaranteed by respecting a minimum EN pulse width after

data transfer.

10.3 Register contents

Table 6 Register bit allocation

CONTROL BITS

ADDRESS

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6

5

4 3210

for test purposes only; all bits must be set to zero for normal operation; this is a forbidden address

0000

for test purposes only; all bits must be set to zero for normal operation; this is a forbidden address

0001

FRAC[15:0]

SYNON 0 1 0 0

CH[8:0]

FR[21:16]

1

SYNON 0 1 0 1

00000

AGC[8:0]

11

RXON 0 1 1 0

0

AFC[11:0]

CKO[1:0] CLKoff CLKon 0 1 1 1

Table 7 Description of symbols used in Table 6

SYNON

RXON

AGC

CH

FRAC

AFC

CLKoff

CKO

SYMBOL

BITS

1

1

9

6

22

12

1

2

DESCRIPTION

3-wire bus

3-wire bus

automatic gain control

integer division ratio for the RF PLL

fractional division ratio for the RF PLL

automatic frequency control for the clock PLL

clock PLL disabled

integer division ratio for the clock PLL

2002 Oct 30

12

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