UAA3220TS Просмотр технического описания (PDF) - Philips Electronics

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UAA3220TS

Frequency Shift Keying (FSK)/Amplitude Shift Keying (ASK) receiver

Philips Electronics 

Philips Semiconductors

Frequency Shift Keying (FSK)/Amplitude

Shift Keying (ASK) receiver

Product specification

UAA3220TS

Table 3 Tests and results

P1 is the maximum available power from signal generator 1 at the input of the test board; P2 is the maximum available

power from signal generator 2 at the input of the test board.

TEST

GENERATOR

1

2

ASK sensitivity into

pin MIXIN (see Fig.5)

FSK sensitivity into

pin MIXIN (see Fig.5)

Maximum input power

for ASK (see Fig.5)

Maximum input power

for FSK (see Fig.5)

Receiver turn-on

time; see note 1 and

Fig.4

Interception point

(mixer + PMA)

see note 2 and Fig.6

modulated test signal 1;

P1 ≤ −113 dBm for

fi(RF) = 433.92 MHz;

P1 ≤ −110 dBm for

fi(RF) = 868.35 MHz

modulated test signal 2;

P1 ≤ −100 dBm

modulated test signal 1;

P1 ≥ −22 dBm

modulated test signal 2;

P1 ≥ −6 dBm

modulated test

signal 1 or 2;

P1 = Pref + 3 dB

test signal 3;

P1 = −40 dBm

−

−

−

−

−

test signal 4;

P2 = P1

Spurious radiation; −

−

see note 3 and Fig.7

RESULT

BER ≤ 3 × 10−2

(e.g. 60 bit errors per second for 2000 bits/s)

BER ≤ 3 × 10−2

(e.g. 60 bit errors per second for 2000 bits/s)

BER ≤ 3 × 10−2

(e.g. 60 bit errors per second for 2000 bits/s)

BER ≤ 3 × 10−2

(e.g. 60 bit errors per second for 2000 bits/s)

check that the first 10 bits are correct;

error counting is started 10 ms after power down

is switched into operating mode on

measure with high impedance probe at pin FA

IP3PMA = P1 + I--M--2---3-- dBm (for IM3 see Fig.6)

no spurious signals (25 MHz to 1 GHz) with level

higher than maximum PSPUR

Notes

1. The voltage at pin PWD of the test circuit alternates between operating mode: on (50 ms; 0 V) and off (138 ms; VCC);

see Fig.4.

2. Probe of spectrum analyzer connected to pin FA (pin 22).

3. Spectrum analyzer connected to the input of the test board.

handbook, full pagewidth VPWD

(V)

2.7

0

0

50

188

238

376

426 t (ms)

MGM745

1999 Jan 22

Fig.4 Timing diagram for pulsed power down voltage.

16

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