5962-0054001Q9A Просмотр технического описания (PDF) - Atmel Corporation

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5962-0054001Q9A

Rad-Hard 32-bit SPARC Embedded Processor

Atmel Corporation 

Run Mode

System Halt Mode

Power Down Mode

Error Halt Mode

Error Handler

Parity Checking

System Clock

System Availability

Test Mode

This RESET output has a minimum of 1024 SYSCLK width to allow the usage of Flash

memories.

The error and Reset Status Register contain the source of the last processor reset.

In this mode the IU/FPU is executing, while all peripherals are running (if software

enabled).

System Halt mode is entered when the SYSHALT input is asserted. In this mode, the IU

and FPU are frozen, while the timers (includeing the internal watchdog timer) and

UART’s are stopped.

This mode is entered by writing to the Power-down Register. In this mode, the IU and

FPU are frozen. The TSC695F leaves the power-down mode if an external interrupt is

asserted.

Error Halt mode is entered under the following circumstances:

– A internal hardware parity error.

– The IU enters error mode.

The only way to exit Error Halt Mode is through Cold Reset by asserting SYSRESET.

The TSC695F has one error output signal (SYSERR) which indicates that an unmasked

error has occurred. Any error signalled on the error inputs from the IU and the FPU is

latched and reflected in the Error and Reset Status Register. By default, an error leads

to a processor halt.

The TSC695F includes:

– Parity checking and generation (if required) on the external data bus

– Parity checking on the external address bus

– Parity checking on ASI and SIZE

– Parity checking and generation on all system registers

– Parity generation and checking on the internal control bus to the IU

All external parity checking can be disabled using the NOPAR signal.

The TSC695F uses CLK2 clock input directly and creates a system clock signal by

dividing CLK2 by two. It drives SYSCLK pin with a nominal 50% duty cycle for the appli-

cation. It is highly recommended that only SYSCLK rising edge is used as reference as

far as possible.

The SYSAV bit in the Error and Reset Status Register can be used by software to indi-

cate system availability.

The TSC695F includes a number of software test facilities such as EDAC test, Parity

test, Interrupt test, Error test and a simple Test Access Port. These test functions are

controlled using the Test Control Register.

12 TSC695F

4118J–AERO–08/04

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