PM4351(2001) Просмотр технического описания (PDF) - PMC-Sierra

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Компоненты Описание

производитель

PM4351
(Rev.:2001)

Combined E1/T1/J1 Transceiver/Framer

PMC-Sierra 

STANDARD PRODUCT

DATA SHEET

PMC-1970624

ISSUE 10

PM4351 COMET

COMBINED E1/T1 TRANSCEIVER

Table 46 - Transmit Test Pattern Modes ..................................................... 225

Table 47 - Transmit Zero Code Suppression Formats ................................ 226

Table 48 - TPSC Indirect Registers 40H-5FH: IDLE Code byte.................. 227

Table 49 - TPSC Indirect Registers 60H-7FH: Signaling/E1 Control byte... 227

Table 50 - Transmit Per-timeslot Data Manipulation ................................... 228

Table 51 - A-Law Digital Milliwatt Pattern.................................................... 228

Table 52 - µ-Law Digital Milliwatt Pattern .................................................... 229

Table 53 - RPSC Indirect Register Map...................................................... 234

Table 54 - RPSC Indirect Registers 20H-3FH: PCM Data Control byte...... 236

Table 55 - Receive Test Pattern Modes ...................................................... 236

Table 56 - RPSC Indirect Registers 40H-5FH: Data Trunk Conditioning Code

byte

238

Table 57 - RPSC Indirect Registers 61H-7FH: Signaling Trunk Conditioning

byte

238

Table 58 - NmNi Settings............................................................................ 249

Table 59 - E1 Signaling Insertion Mode ...................................................... 250

Table 60 - E1 Timeslot 0 Bit 1 Insertion Control Summary ......................... 252

Table 61 - National Bits Codeword Select .................................................. 262

Table 62 - Timeslot 0 Bit Position Allocation ............................................... 278

Table 63 - Signaling Multiframe Timeslot 16, Frame 0 Bit Positions ........... 282

Table 64 - E1 FRMR Codeword Select....................................................... 284

Table 65 - Receive Packet Byte Status....................................................... 302

Table 66 - Clock Synthesis Mode ............................................................... 308

Table 67 - Pattern Detector Register Configurations .................................. 315

Table 68 - Error Insertion Rates.................................................................. 321

PROPRIETARY AND CONFIDENTIAL

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