TMP86FS49AIFG Просмотр технического описания (PDF) - Toshiba
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TMP86FS49AIFG Datasheet PDF : 296 Pages
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TMP86FS49AIFG
2. Operational Description
2.1 CPU Core Functions
The CPU core consists of a CPU, a system clock controller, and an interrupt controller.
This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.
2.1.1 Memory Address Map
The TMP86FS49AIFG memory is composed Flash, RAM, DBR(Data buffer register) and SFR(Special
function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the TMP86FS49AIFG
memory address map.
SFR
0000H
003FH
0040H
RAM
083FH
DBR
0F80H
0FFFH
1000H
64 bytes
2048
bytes
128
bytes
SFR:
RAM:
Special function register includes:
I/O ports
Peripheral control registers
Peripheral status registers
System control registers
Program status word
Random access memory includes:
Data memory
Stack
DBR: Data buffer register includes:
Peripheral control registers
Peripheral status registers
Flash: Program memory
Flash
FFB0H
FFBFH
FFC0H
FFDFH
FFE0H
FFFFH
61440
bytes
Vector table for interrupts
(16 bytes)
Vector table for vector call instructions
(32 bytes)
Vector table for interrupts
(32 bytes)
Figure 2-1 Memory Address Map
2.1.2 Program Memory (Flash)
The TMP86FS49AIFG has a 61440 bytes (Address 1000H to FFFFH) of program memory (Flash ).
2.1.3 Data Memory (RAM)
The TMP86FS49AIFG has 2048 bytes (Address 0040H to 083FH) of internal RAM. The first 192 bytes
(0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are
available against such an area.
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