74VHC4046CW Просмотр технического описания (PDF) - Fairchild Semiconductor

Номер в каталоге

Компоненты Описание

производитель

74VHC4046CW

CMOS Phase Lock Loop

Fairchild Semiconductor 

Detailed Circuit Description (Continued)

Phase comparator II is more susceptible to noise causing

the phase lock loop to unlock. If a noise pulse is seen on

the signal input, the comparator treats it as another positive

edge of the signal and will cause the output to go HIGH

until the VCO leading edge is seen, potentially for a whole

signal input period. This would cause the VCO to speed up

during that time. When using the phase comparator I the

output of that phase detector would be disturbed for only

the short duration of the noise spike and would cause less

upset.

PHASE COMPARATOR III

This comparator is a simple S-R Flip-Flop which can func-

tion as a phase comparator Figure 7. It has some similar

characteristics to the edge sensitive comparator. To see

how this detector works assume input pulses are applied to

the signal and comparator inputs as shown in Figure 8.

When the signal input leads the comparator input the flop is

set. This will charge up the loop filter and cause the VCO to

speed up, bringing the comparator into phase with the sig-

nal input. When using short pulses as input this comparator

behaves very similar to the second comparator. But one

can see that if the signal input is a long pulse, the output of

the comparator will be forced to a one no matter how many

comparator input pulses are received. Also if the VCO input

is a square wave (as it is) and the signal input is pulse then

the VCO will force the comparator output LOW much of the

time. Therefore it is ideal to condition the signal and com-

parator input to short pulses. This is most easily done by

using a series capacitor.

FIGURE 7. Phase Comparator III Logic Diagram

FIGURE 8. Typical Waveforms for Phase Comparator III

13

www.fairchildsemi.com

Share Link: