AM79C90 Просмотр технического описания (PDF) - Advanced Micro Devices

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AM79C90

CMOS Local Area Network Controller for Ethernet (C-LANCE)

Advanced Micro Devices 

Bit

Name

Description

PRELIMINARY

Bit

Name

Description

AMD

11

MERR

MEMORY ERROR is set when the

07

C-LANCE is the Bus Master and has

not received READY within 25.6 µs

after asserting the address on the

DAL lines.

INTR

INTERRUPT FLAG is set by the

“ORing” of BABL, MISS, MERR,

RINT, TINT and IDON. If INEA = 1

and INTR = 1, the INTR pin will be

LOW.

When a Memory Error is detected,

the receiver and transmitter are

turned off (CSR0, TXON = 0, RXON

= 0) and an interrupt is generated if

INEA = 1.

INTR is READ ONLY; writing this bit

has no effect. INTR is cleared by

RESET, by setting the STOP bit, or

by clearing the condition causing the

interrupt.

MERR is READ/CLEAR ONLY, and

06

INEA

INTERRUPT ENABLE allows the

is set by the C-LANCE and cleared

INTR pin to be driven LOW when the

by writing a “1” into the bit. Writing a

Interrupt Flag is set. If INEA = 1 and

“0” has no effect. It is cleared by

INTR = 1, the INTR pin will be Low. If

RESET or by setting the STOP bit.

INEA = 0, the INTR pin will be HIGH,

10

RINT

RECEIVER INTERRUPT is set

when the C-LANCE updates an en-

regardless of the state of the Inter-

rupt Flag.

try in the Receive Descriptor Ring for

INEA is READ/WRITE and cleared

the last buffer received or reception

by RESET or by setting the STOP

is stopped due to a failure.

bit.

When RINT is set, an interrupt is

INEA can be set at any time, regard-

generated if INEA = 1.

less of the state of the STOP bit.

RINT is READ/CLEAR ONLY, and is

(reference Appendix B).

set by the C-LANCE and cleared by

05

RXON RECEIVER ON indicates that the re-

writing a “1” into the bit. Writing a “0”

ceiver is enabled. RXON is set when

has no effect. It is cleared by RESET

STRT is set if DRX = 0 in the MODE

or by setting the STOP bit.

register in the initialization block and

09

TINT

TRANSMITTER INTERRUPT is set

when the C-LANCE updates an en-

try in the transmit descriptor ring for

the last buffer sent or transmission is

stopped due to a failure.

the initialization block has been read

by the C-LANCE by setting the INIT

bit. RXON is cleared when IDON is

set from setting the INIT bit and DRX

= 1 in the MODE register, or a mem-

ory error (MERR) has occurred.

When TINT is set, an interrupt is

RXON is READ ONLY; writing this

generated if INEA = 1.

TINT is READ/CLEAR ONLY and is

bit has no effect. RXON is cleared by

RESET or by setting the STOP bit.

set by the C-LANCE and cleared by

04

TXON

TRANSMITTER ON indicates that

writing a “1” into the bit. Writing a “0”

has no effect. It is cleared by RESET

the transmitter is enabled. TXON is

set when STRT is set if DTX = 0 in

or by setting the STOP bit.

the MODE register in the initializa-

08

IDON

INITIALIZATION DONE indicates

that the C-LANCE has completed

the initialization procedure started

by setting the INIT bit. When IDON is

set, the C-LANCE has read the In-

itialization Block from memory and

tion block and the INIT bit has been

set. TXON is cleared when IDON is

set and DTX = 1 in the MODE regis-

ter, or an error, such as MERR,

UFLO or BUFF, has occurred during

transmission.

stored the new parameters.

TXON is READ ONLY; writing this bit

When IDON is set, an interrupt is

generated if INEA = 1.

has no effect. TXON is cleared by

RESET or by setting the STOP bit.

IDON is READ/CLEAR ONLY, and is

set by the C-LANCE and cleared by

writing a “1” into the bit. Writing a “0”

has no effect. It is cleared by RESET

or by setting the STOP bit.

Am79C90

21

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