TDA7562 Просмотр технического описания (PDF) - STMicroelectronics

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TDA7562

MULTIFUNCTION QUAD POWER AMPLIFIER WITH BUILT-IN DIAGNOSTICS FEATURES

STMicroelectronics 

TDA7562

I2C BUS INTERFACE

Data transmission from microprocessor to the

TDA7562 and viceversa takes place through the

2 wires I2C BUS interface, consisting of the two

lines SDA and SCL (pull-up resistors to positive

supply voltage must be connected).

Data Validity

As shown by fig. 16, the data on the SDA line

must be stable during the high period of the clock.

The HIGH and LOW state of the data line can

only change when the clock signal on the SCL

line is LOW.

Start and Stop Conditions

As shown by fig. 17 a start condition is a HIGH to

LOW transition of the SDA line while SCL is

HIGH.

The stop condition is a LOW to HIGH transition of

the SDA line while SCL is HIGH.

Byte Format

Every byte transferred to the SDA line must con-

tain 8 bits. Each byte must be followed by an ac-

knowledge bit. The MSB is transferred first.

Acknowledge

The transmitter* puts a resistive HIGH level on the

SDA line during the acknowledge clock pulse (see

fig. 18). The receiver** the acknowledges has to

pull-down (LOW) the SDA line during the acknow-

ledge clock pulse, so that the SDAline is stable

LOW during this clock pulse.

* Transmitter

= master (µP) when it writes an address to

the TDA7562

= slave (TDA7562) when the µP reads a

data byte from TDA7562

** Receiver

= slave (TDA7562) when the µP writes an

address to the TDA7562

= master (µP) when it reads a data byte from

TDA7562

Figure 16: Data Validity on the I2CBUS

SDA

SCL

DATA LINE

STABLE, DATA

VALID

Figure 17: Timing Diagram on the I2CBUS

CHANGE

DATA

ALLOWED

SCL

SDA

START

Figure 18: Acknowledge on the I2CBUS

D99AU1032

SCL

1

2

3

7

SDA

START

MSB

D99AU1033

D99AU1031

I2CBUS

STOP

8

9

ACKNOWLEDGMENT

FROM RECEIVER

11/17

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